Utilizing Backside Irradiation Patents (Class 438/160)
  • Patent number: 10379413
    Abstract: This present disclosure provides an array substrate, a manufacturing method thereof, and a display apparatus, aiming at solving the issue of light reflection on the array substrates and improving the display effects of display apparatuses. The array substrate includes a transparent substrate; a plurality of components disposed on a first side of the transparent substrate; and a shielding pattern, disposed on a second side of the transparent substrate, and configured to shield light reflected from a surface of at least one of the plurality of components.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 13, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shoukun Wang, Liangliang Li, Yuchun Feng, Huibin Guo
  • Patent number: 10128278
    Abstract: A thin film transistor substrate includes a switching element comprising a gate electrode electrically connected to a gate line extending in a first direction, an active pattern overlapping with the gate electrode, a source electrode disposed on the active pattern and electrically connected to a data line extending in a second direction crossing the first direction, and a drain electrode spaced apart from the source electrode. The thin film transistor substrate further includes an organic layer disposed on the switching element, a first electrode disposed on the organic layer, and a second electrode overlapping with the first electrode, and electrically connected to the drain electrode. A thickness of the second electrode is thicker than a thickness of the first electrode.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Yong Kim, Woong-Ki Jeon, Hyun-Jin Kim, Jean-Ho Song
  • Patent number: 9893098
    Abstract: Embodiments of the present disclosure provide an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate includes: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate. The forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film and a source-drain metal film on the base substrate; forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process. The number of the exposing process is reduced, the production cycle is shortened and the fabrication cost is reduced.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: February 13, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jian Guo
  • Patent number: 9754978
    Abstract: A semiconductor device (1001) includes: a first transistor (10A) having a first channel length L1 and a first channel width W1; and a second transistor (10B) having a second channel length L2 and a second channel width W2, wherein the first transistor (10A) and the second transistor (10B) include an active layer formed from a common oxide semiconductor film, the first transistor (10A) is a memory transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Isd depends on a gate voltage Vg to a resistor state where the drain current Isd does not depend on the gate voltage Vg, and the first channel length L1 is smaller than the second channel length L2.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 5, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Ueda, Sumio Katoh
  • Patent number: 9645457
    Abstract: An array substrate has regions in which an intermediate resist film thickness is formed and processed by an intermediate exposure amount which does not completely expose a resist, respectively on a drain electrode, source terminal, and a common connection wiring which are made of a second conductive film. Thin film patterns or a common wiring made of a first conductive film is formed in substantially entire regions on the bottom layers of the regions so that the heights from a substrate are substantially the same.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 9, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Masutani, Shigeaki Noumi, Takeshi Shimamura, Masaru Aoki
  • Patent number: 9576989
    Abstract: An array substrate and the method for making the same, and a display device are provided. The method includes step 1, forming a pattern comprising a gate electrode and a gate line on a substrate, and providing photoresist at a position reserved for a first via hole above the gate line in a non-display area; step 2, forming a pattern of functional layers of a thin film transistor (TFT) and a data line on the substrate after the above step; step 3, forming a pattern comprising a first pixel electrode on the substrate after the above steps, and then forming a passivation layer; step 4, removing the photoresist provided above the position reserved for the first via hole and film layer thereabove from the substrate after the above steps, so as to form the first via hole.
    Type: Grant
    Filed: April 27, 2013
    Date of Patent: February 21, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Qin, Wenqi Li
  • Patent number: 9466624
    Abstract: Embodiments of the present disclosure provide an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate includes: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate. The forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film and a source-drain metal film on the base substrate; forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process. The number of the exposing process is reduced, the production cycle is shortened and the fabrication cost is reduced.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 11, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jian Guo
  • Patent number: 9419066
    Abstract: To provide a bright and highly reliable light-emitting device. An anode (102), an EL layer (103), a cathode (104), and an auxiliary electrode (105) are formed sequentially in lamination on a reflecting electrode (101). Further, the anode (102), the cathode (104), and the auxiliary electrode (105) are either transparent or semi-transparent with respect to visible radiation. In such a structure, lights generated in the EL layer (103) are almost all irradiated to the side of the cathode (104), whereby an effect light emitting area of a pixel is drastically enhanced.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 16, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Fukunaga, Junya Maruyama
  • Patent number: 9202929
    Abstract: An object is to increase the on-state current of a thin film transistor. A solution is to provide a projection in a back-channel portion of the thin film transistor. The projection is provided so as to be off a tangent in the back-channel portion between a source or a drain and a channel formation region. With the projection, a portion where electric charge is trapped and a path of the on-state current can be apart from each other, so that the on-state current can be increased. The shape of a side surface of the back-channel portion may be curved, or may be represented as straight lines in a cross section. Further, a method for forming such a shape by performing one etching step is provided.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hideomi Suzawa, Hiromichi Godo, Shinya Sasagawa
  • Patent number: 9116430
    Abstract: In the proposed plasmonic nanolithography technique a transparent mask is brought into physical contact with a metal on a substrate that is coated with a photoresist. The mask is not made of metal or other material that supports surface plasmons. The metal layer is exposed to radiation of a characteristic vacuum wavelength through the mask and the photoresist or through the substrate. The mask features and the vacuum wavelength of the radiation are chosen so that the radiation excites surface plasmons at the interface between the metal and the photoresist. The excitation of surface plasmons allows for the exposure and generation of features which are well-below the free space diffraction limit and small compared to the size of the features in the mask.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 25, 2015
    Assignee: Rolith, Inc.
    Inventors: Boris Kobrin, Edward Barnard
  • Patent number: 9117915
    Abstract: A thin film transistor (TFT) that includes a gate, an oxide semiconductor layer, a gate insulator, a source, and a drain is provided. The gate insulator is located between the oxide semiconductor layer and the gate. The source and the drain are in contact with different portions of the oxide semiconductor layer. Each of the source and the drain has a ladder-shaped sidewall that is partially covered by the oxide semiconductor layer. A method for fabricating the above-mentioned TFT is also provided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 25, 2015
    Assignee: Au Optronics Corporation
    Inventors: Chang-Ming Lu, Lun Tsai, Chia-Yu Chen
  • Patent number: 8987743
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: March 24, 2015
    Assignees: Boe Technology Group Co., Ltd., Hefei Boe Optoelectroncis Technology Co., Ltd.
    Inventor: Yunqi Zhang
  • Patent number: 8981516
    Abstract: A back-side illuminated image sensor formed from a thinned semiconductor substrate, wherein: a transparent conductive electrode, insulated from the substrate by an insulating layer, extends over the entire rear surface of the substrate; and conductive regions, insulated from the substrate by an insulating coating, extend perpendicularly from the front surface of the substrate to the electrode.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 17, 2015
    Assignees: STMicroeletronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Jens Prima, Fran├žois Roy, Michel Marty
  • Patent number: 8980704
    Abstract: A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: March 17, 2015
    Assignee: Ye Xin Technology Consulting Co., Ltd.
    Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8962405
    Abstract: In some aspects of the invention, a circuit pattern of a front surface structure is formed in a front surface of a semiconductor wafer and an alignment mark is formed on the front surface of a semiconductor wafer. A transparent supporting substrate is attached to the front surface of the semiconductor wafer by a transparent adhesive. Then, a resist is applied onto a rear surface of the semiconductor wafer. Then, the semiconductor wafer is mounted on a stage of an exposure apparatus, with the supporting substrate down. Then, the alignment mark formed on the front surface of the semiconductor wafer is recognized by a camera, and the positions of the semiconductor wafer and a photomask are aligned with each other. Then, the resist is patterned. Then, a circuit pattern is formed in the rear surface of the semiconductor wafer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tsunehiro Nakajima, Haruo Nakazawa
  • Patent number: 8878175
    Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8823001
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 2, 2014
    Assignees: Boe Technology Group Co., Ltd., Hefei Boe Optoelectronics Technology Co., Ltd.
    Inventor: Yunqi Zhang
  • Patent number: 8802514
    Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernst-August Haensch, Zihong Liu
  • Patent number: 8796692
    Abstract: A thin-film semiconductor device includes: a gate electrode; a channel layer; a first amorphous semiconductor layer; a channel protective layer; a pair of second amorphous semiconductor layers formed on side surfaces of the channel layer; and a pair of contact layers which contacts the side surfaces of the channel layer via the second amorphous semiconductor layers. The gate electrode, the channel layer, the first amorphous semiconductor layer, and the channel protective layer are stacked so as to have outlines that coincide with one another in a top view. The first amorphous semiconductor layer has a density of localized states higher than those of the second amorphous semiconductor layers. The second amorphous semiconductor layers have band gaps larger than that of the first amorphous semiconductor layer.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Panasonic Corporation
    Inventors: Arinobu Kanegae, Takahiro Kawashima
  • Patent number: 8748222
    Abstract: A method for manufacturing oxide thin film transistors includes steps of: forming a gate, a drain electrode, a source electrode, and an oxide semiconductor layer respectively. The oxide semiconductor layer is formed on the gate electrode; the drain electrode and the source electrode are formed at two opposite sides of the oxide semiconductor layer. The method further includes a step of depositing a dielectric layer of silicon oxide, and a reacting gas for depositing the silicon oxide includes silane and nitrous oxide. A flow rate of nitrous oxide is in a range from 10 to 200 standard cubic centimeters per minute (SCCM). Oxide thin film transistors manufactured by above method has advantages of low leakage, high mobility, and other integrated circuit member can be directly formed on the thin film transistor array substrate of a display device.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 10, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Ted-Hong Shinn, Henry Wang, Fang-An Shu, Yao-Chou Tsai
  • Patent number: 8703560
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8691639
    Abstract: Embodiments of the disclosed technology disclose manufacture methods of a thin film transistor and an array substrate and a mask therefor are provided. The manufacture method of the thin film transistor comprises: patterning a wire layer by using a exposure machine and a mask with a first exposure amount larger than a normal exposure amount during formation of source and drain electrodes; forming a semiconductor layer on the patterned wire layer; patterning the semiconductor layer by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount. The mask comprises a source region for forming the source electrode, a drain region for forming the drain electrode and a slit provided between the source region and the drain region, and the width of the slit is smaller than the resolution of the exposure machine.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 8, 2014
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Weifeng Zhou, Jianshe Xue
  • Patent number: 8647934
    Abstract: A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: February 11, 2014
    Assignee: Au Optronics Corporation
    Inventors: Liu-Chung Lee, Hung-Che Ting, Chia-Yu Chen
  • Patent number: 8575714
    Abstract: Provided is a backside illuminated semiconductor light-receiving device enhancing a frequency characteristic without deteriorating assembling operability. The light-receiving device includes a rectangular substrate; a light receiving mesa portion formed on a center portion of one side on a front surface of the substrate and includes a PN junction portion; a P-type electrode formed on the light receiving mesa portion and conductive with one side of the PN junction portion; an N-type electrode mesa portion formed on one corner portion of the one side; an N-type electrode pulled out to the N-type electrode mesa portion and conductive with the other side of the PN junction portion; a P-type electrode mesa portion and a dummy electrode mesa portion formed in a region including three other corner portions; and a dummy electrode formed on the dummy electrode mesa portion.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Oclaro Japan, Inc.
    Inventors: Takashi Toyonaka, Hiroshi Hamada, Masataka Yokosawa
  • Patent number: 8569121
    Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernst-August Haensch, Zihong Liu
  • Patent number: 8546179
    Abstract: A method of fabricating a self-aligned top-gate organic transistor comprises depositing a photoresist material over the dielectric material, and exposing the photoresist material to irradiation through the substrate using the source and drain electrodes as a mask. The exposure defines a region for deposition of the gate electrode.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: October 1, 2013
    Assignee: Cambridge Display Technology Ltd.
    Inventor: Euan Smith
  • Patent number: 8501554
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8502221
    Abstract: An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: August 6, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8501553
    Abstract: A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride , the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: August 6, 2013
    Assignee: Hannstar Display Corp.
    Inventors: Hsien Tang Hu, Chien Chih Hsiao, Chih Hung Tsai
  • Patent number: 8492190
    Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 23, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Ae Youn, Yang-Ho Bae, Chang-Oh Jeong, Chong-Chul Chai, Pil-Sang Yun, Honglong Ning, Byeong-Beom Kim
  • Patent number: 8492212
    Abstract: Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: July 23, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tokuaki Kuniyoshi, Hidehito Kitakado, Tadayoshi Miyamoto, Kazuhide Tomiyasu, Sumio Katoh
  • Patent number: 8450160
    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil Soon Hong, Gwui-Hyun Park, Sang Gab Kim
  • Patent number: 8445339
    Abstract: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: May 21, 2013
    Assignee: AU Optronics Corp.
    Inventors: Hantu Lin, Chienhung Chen
  • Patent number: 8436358
    Abstract: Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R?W is satisfied.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: May 7, 2013
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Yoshiaki Toyota
  • Patent number: 8435823
    Abstract: According to one embodiment, a method of manufacturing a back-illuminated solid-state imaging device including forming a mask with apertures corresponding to a pixel pattern on the surface of a semiconductor layer, implanting second-conductivity-type impurity ions into the semiconductor layer from the front side of the layer to form second-conductivity-type photoelectric conversion parts and forming a part where no ion has been implanted into a pixel separation region, forming at the surface of the semiconductor layer a signal scanning circuit for reading light signals obtained at the photoelectric conversion parts after removing the mask, and removing the semiconductor substrate and a buried insulating layer from the semiconductor layer after causing a support substrate to adhere to the front side of the semiconductor layer.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Yamashita
  • Patent number: 8435832
    Abstract: A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: May 7, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 8405086
    Abstract: The present invention provides a pixel structure of a display panel and a method for manufacturing the same. The method comprises the following steps: forming a first transistor and a second transistor on a substrate, wherein the first transistor is connected between the second transistor and a data line, wherein the second transistor is connected to a first gate line and a second gate line; and forming a pixel electrode, wherein the pixel electrode is connected to the first transistor. The present invention can improve a deformation problem of signal waveforms due to delay.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: March 26, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Hung-lung Hou
  • Patent number: 8378352
    Abstract: An organic light-emitting display device and a method of manufacturing the organic light-emitting display device are disclosed. The organic light-emitting display device includes a bottom capacitor electrode that is formed over the same plane as an active layer of a thin film transistor and includes a semiconductor doped with ion impurities, a pixel electrode, and a top capacitor electrode formed over the same plane as a gate electrode, wherein a contact hole entirely exposing the pixel electrode and the top capacitor electrode is formed.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 19, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yul-Kyu Lee, Chuy-Gi You, Sun Park, Jong-Hyun Park, Dae-Woo Kim
  • Patent number: 8349671
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8309407
    Abstract: Methods in accordance with aspects of this invention form microelectronic structures in accordance with other aspects of this invention, such as non-volatile memories, that include (1) a layerstack having a pattern including sidewalls, the layerstack comprising a resistivity-switchable layer disposed above and in contact with a bottom electrode, and a top electrode disposed above and in contact with the resistivity-switchable layer; and (2) a dielectric sidewall liner in contact with the sidewalls of the layerstack; wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material. Numerous additional aspects are provided.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 13, 2012
    Assignee: SanDisk 3D LLC
    Inventor: April D. Schricker
  • Patent number: 8273600
    Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: September 25, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Patent number: 8207535
    Abstract: The present invention relates to a thin film transistor substrate. The thin film transistor according to one embodiment of the present invention comprises: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a thin film transistor formed on the intersection of the gate wire and the data wire; an inorganic insulating layer covering the thin film transistor and having a surface that a prominence and depression pattern formed on; and a reflective layer provided on the prominence and depression pattern. Thus, the present invention provides a thin film transistor substrate which reduces the time required in the process and enhance the productivity.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 26, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Hyun-Ho Kim
  • Publication number: 20120149158
    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.
    Type: Application
    Filed: March 29, 2011
    Publication date: June 14, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Soon HONG, Gwui-Hyun PARK, Sang Gab KIM
  • Patent number: 8138087
    Abstract: An integrated circuit is provided that comprises a substrate of silicon and an interconnect in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallization layer on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: March 20, 2012
    Assignee: NXP B.V.
    Inventors: Stephane Morel, Arnoldus Den Dekker, Elisabeth C. Rodenburg, Eric C. E. Van Grunsven
  • Publication number: 20110212581
    Abstract: An array substrate for a liquid crystal display device comprises a substrate having a pixel region, a gate line on the substrate, and a data line crossing the gate line to define the pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, an insulating layer on the gate electrode, an active layer on the insulating layer, an ohmic contact layer on the active layer, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode. A pixel electrode connects to the drain electrode and is disposed in the pixel region. An opaque metal pattern is provided on end portions of the pixel electrode.
    Type: Application
    Filed: May 11, 2011
    Publication date: September 1, 2011
    Inventors: Ji-Hyun Jung, Dong-Young Kim
  • Patent number: 8003451
    Abstract: The embodiment of the invention discloses an exemplary method, in which a gate line, a gate electrode, and a pixel electrode are formed in a first step; a multilayer structure is formed on the gate line and the gate electrode in a second step; and a data line and source/drain electrodes are formed in a third step.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 23, 2011
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventor: Youngjin Song
  • Patent number: 7977151
    Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: July 12, 2011
    Assignee: Cbrite Inc.
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 7977176
    Abstract: A flexible display device for improving reliability, and a fabricating method thereof are disclosed. In the method of fabricating the flexible display device, an insulating protective layer is formed at one side of a glass substrate. A display device including a thin film transistor array and a pad part, which is connected to the thin film transistor array, is formed on the insulating protective layer. A flexible substrate is attached on the display device. And the glass substrate is removed.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 12, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Eui Yool Oh
  • Patent number: 7951702
    Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: May 31, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree