Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: A chip quality determination method includes the steps of (a) determining the continuity of defective chips in at least four directions of an X-axis and a Y-axis on a wafer based on the wafer test result of determining the acceptability of chips arranged in a matrix in the four directions on the wafer, and dividing the defective chips into one or more defective groups so that successive ones of the defective chips are in the same defective group; (b) calculating a quality determination index of each of one or more determination target wafer periphery neighboring chips among wafer periphery neighboring chips located within a predetermined range from the periphery of the wafer based on the distance from a corresponding one of the defective groups; and (c) determining the quality of the determination target wafer periphery neighboring chips by comparing the quality determination indexes thereof with a preset threshold.

Abstract: This present invention discloses a manufacturing method and structure for a wafer level image sensor module with fixed focal length. The method includes the following steps. First, a silicon wafer comprising several image sensor chips having a photosensitive area and a lens module array wafer comprising several wafer level lens modules with fixed focal length are provided. Next, the image sensor chips and the wafer level lens modules are sorted in grades according to the different quality grades. According to the sorting results, each of the wafer level lens modules is assigned to be situated above the image sensor chip that has the same grade. At the same time, each of the wafer level lens modules is directed to face the photosensitive area of each image sensor chip. Finally, in the packaging process, the wafer level lens module is surrounded by an encapsulation material.

Abstract: The manufacturing efficiency of semiconductor devices is improved. A plurality of external terminals (leads) electrically coupled with a semiconductor chip, and contact regions of a plurality of terminals (test terminals) are brought into contact with each other, respectively. This establishes an electrical coupling between the semiconductor chip and a test circuit. Thus, an electrical test is performed. Herein, the terminals are to be repeatedly used in the electrical test of a plurality of semiconductor devices. Whereas, the contact region of the terminal includes a core material formed of a first alloy, and a metal film covering the core material. Further, the metal film is formed of a second alloy higher in hardness than the first alloy.

Abstract: A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Abstract: Circuit modules including identification codes and a method of managing them are provided. A module substrate includes signal input output terminals and outer ground terminals provided at the peripheral portions of a surface which becomes a mounting surface when the circuit module is completed. An inner-ground-terminal formation area surrounded by the signal input output terminals and the outer ground terminals includes a plurality of inner ground terminals arranged in a matrix of rows and columns. One of the edge portions is a direction identification area. The inner ground terminal is not provided in the direction identification area, and a first identification code having information about the position of the module substrate is provided in the direction identification area.

Abstract: A method of manufacturing a semiconductor device which solves a problem with a burn-in process where current and voltage are applied to finished semiconductor devices at high-temperature. The method uses an organic multilayer wiring substrate for a burn-in board in which power supply/grounding wiring is formed with microscopic openings formed at least almost all over the areas around sockets over the front or back surface of the substrate. For increasing the supply voltage and reference voltage for the burn-in board and other purposes, whenever possible, signal wires are disposed in inner wiring layers of the board. The related-art burn-in board which has a solid or blanket-type conductor pattern in an outermost layer as wiring for supply or reference voltage may cause an insulating protective film over the metal wiring to peel due to weak adhesion between the wiring and film when thermal cycles are repeated. The method solves the problem.

Abstract: The present invention provides a radiation image pickup apparatus in which one or more image pickup elements are easily exchanged. A radiation image pickup apparatus includes a base, at least one image pickup element, a scintillator, a first heat peelable adhesive layer which is arranged between the base and the image pickup element and which fixes the base and the image pickup element, and a second heat peelable adhesive layer which is arranged between the image pickup element and the scintillator and which fixes the image pickup element and the scintillator, and in the radiation image pickup element described above, the first heat peelable adhesive layer contains first heat-expandable microspheres, the second heat peelable adhesive layer contains second heat-expandable microspheres, and the first heat-expandable microspheres have a different expansion starting temperature from that of the second heat-expandable microspheres.

Abstract: A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: An electronic component mounting apparatus is capable of significantly reducing a warpage amount of an electronic component warped in a case of thermocompression bonding using a non-conductive adhesive agent having a low minimum melt viscosity and having no conductive particle where a thin electronic component having a thickness smaller than or equal to 200 ?m is mounted on a wiring board. In the mounting apparatus, a non-conductive adhesive film having the minimum melt viscosity lower than or equal to 1.0×103 Pa·s is placed on a wiring board placed on a base, and an IC chip having a thickness smaller than or equal to 200 ?m is placed on the non-conductive adhesive film. In the mounting apparatus, the IC chip is pressurized by a thermocompression bonding head having a compression bonding portion made of elastomer having a rubber hardness lower than or equal to 60, so that the IC chip is bonded onto the wiring board by thermocompression.

Abstract: Embodiments relate to Hall-controlled switch devices. In an embodiment, a Hall switch and a load switch are integrated in a single integrated circuit device. Embodiments can provide load switching and optional simultaneous logic signaling, for example to update a microcontroller or electronic control unit (ECU), while reducing space and complexity and thereby cost.

Abstract: There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates.

Abstract: Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.

Abstract: A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a protection material; the method envisages: detecting electrical values generated by the MEMS devices in response to at least a testing stimulus; and, before the step of detecting, at least partially separating contiguous MEMS devices in the strip. The step of separating includes defining a separation trench between the contiguous MEMS devices, the separation trench extending through the whole thickness of the protection material and through a surface portion of the substrate, starting from the internal surface of the substrate.

Abstract: A wafer-level optical deflector assembly is formed on a front surface side of a wafer. Then, the front surface side of the wafer is etched by using elements of the wafer-level optical deflector assembly, to form a front-side dicing street. Then, a transparent substrate with an inside cavity is adhered to the front surface side of the wafer. Then, a second etching mask is formed on a back surface side of the wafer. Then, the back surface side of the wafer is etched to create a back-side dicing street. Then, an adhesive sheet with a ring-shaped rim is adhered to the back surface side of the wafer. Then, the transparent substrate is removed. Finally, the ring-shaped rim is expanded to widen the front-side dicing street and the back-side dicing street to pick up optical deflectors one by one from the wafer.

Abstract: An LED packaging method includes: providing a mold with two isolated receiving spaces and a substrate with a die supporting portion and an electrode portion respectively received in the two receiving spaces; disposing an LED die on the die supporting portion and electrically connecting the LED die to the electrode portion of the substrate by metal wires; injecting a light wavelength converting material into the first receiving space and covering the LED die with the light wavelength converting material; communicating the first receiving space to the second receiving space, injecting a first light transmissive material into the communicated first and second spaces, and covering the light wavelength converting material and the metal wires with the first light transmissive material; and removing the mold to obtain a packaged LED.

Abstract: An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card.

Abstract: A surface mount type semiconductor device is disclosed. The semiconductor device has testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon. Lower surface-side lands with solder balls coupled thereto respectively and testing lands with solder balls not coupled thereto are formed on a lower surface of a wiring substrate. To suppress the occurrence of contact imperfection between the testing lands and land contacting contact pins provided in a probe socket, the diameter of each testing land is set larger than the diameter of each lower surface-side land. Even when the wiring substrate is reduced in size, electrical characteristic tests using the testing lands can be done with high accuracy.

Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: With a die bonder or a bonding method, the die is adsorbed by the collet, the dicing tape to which the die is adsorbed is thrust up, the die adsorbed by the collet, and thrust up is peeled from the dicing tape, and the peeled die is bonded to the substrate. When the decrease in the air leak flow rate through the gap between the collet and the die upon the thrust up is smaller than the decrease in the normal peel by a predetermined amount, it is judged that a deflection occurs in the die.

Abstract: A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip.

Abstract: A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns.

Abstract: An energy distribution of soft error-inducing radiation likely to be encountered by an electronic circuit during operation is determined. A tuned radiation source having a source energy distribution similar to the determined energy distribution is prepared. The electronic circuit is tested using the tuned radiation source.

Abstract: A method is provided for laser patterning an integrated circuit (IC) etching mask. The method provides an IC packaged die with a first region underlying a backside surface of a bulk silicon (Si) layer. An etch-resistant film is formed overlying the backside surface. Alternately, the entire IC die package is conformally coated. A semi-transparent film is formed overlying the etch-resistant film, semi-transparent to light having a first wavelength. In response to irradiating the semi-transparent film with light having a first power density, an IC die first region is located. In response to irradiating the semi-transparent film with a laser light having a second power density, greater than the first power density, an area of etch-resistant film overlying the first region is decomposed. More explicitly, an area of semi-transparent film overlying the first region is ablated, and the etch-resistant film underlying the ablated semi-transparent film is heated.

Abstract: A laminated module or panel of solar cells and a laminating method for making same comprise a top layer of melt flowable optically transparent molecularly flexible thermoplastic and a rear sheet of melt flowable insulating molecularly flexible thermoplastic both melt flowing at a temperature between about 80° C. and 250° C. and having a low glass transition temperature. Solar cells are encapsulated by melt flowing the top layer and rear sheet, and electrical connections are provided between front and back contacts thereof. Light passing through the transparent top layer impinges upon the solar cells and the laminated module exhibits sufficient flexural modulus without cross-linking chemical curing. Electrical connections may be provided by melt flowable electrically conductive molecularly flexible thermoplastic adhesive or by metal strips or by both.

Abstract: In a method for producing a semi-conductor module (10) comprising at least two semi-conductor chips (12, 14) and an interposer (20) which has electrically conductive structures (28) connecting the semi-conductor chips (12, 14) to one another, the interposer (20) is printed directly onto a first (12) of the semi-conductor chips. When the interposer (20) is printed on, the electrically conductive structures (28) are produced by means of electrically conductive ink (68). The second semi-conductor chip (14) is mounted on the interposer (20) such that the two semi-conductor chips (12, 14) are arranged one above the other and that the interposer (20) forms an intermediate layer between the two semi-conductor chips (12, 14).

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

Abstract: In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.

Abstract: A device for resin coating is used for producing an LED package including an LED element covered with resin containing phosphor. In a state in which a trial coating material 43 is located by a clamp unit 63, a trial coating of resin applied to the trial coating material 43 is irradiated with excitation light and light emitted from the phosphor contained in the resin is measured by an emission characteristic measuring unit 39. A deviation of the measurement result of the emission characteristic measuring unit from a prescribed emission characteristic is determined, and then a proper amount of resin to be applied to the LED element is derived for actual production based on the deviation.

Abstract: An entangled photon pair source including: a quantum emitter having a ground state, two degenerate states that have one elementary excitation and different spins, and a state having two elementary excitations; a first optical cavity, wherein the quantum emitter is inserted; and a second optical cavity coupled with the first cavity. The geometry of the first and second cavities, and force of coupling thereof, are selected such that the whole formed by both coupled cavities has a first pair of polarization-degenerate modes, that are resonant with transitions between the state having two elementary excitations and the two degenerate states having one elementary excitation from the quantum emitter, and a second pair of polarization-degenerate modes that are resonant with transitions between the degenerate states, having one elementary excitation, and the ground state.

Abstract: The present invention provides an apparatus and method for rapid and uniform thermal treatment of semiconductor workpieces in two closely arranged thermal treatment chambers with a retractable door between them. The retractable door moves in between two thermal treatment chambers during heating or cooling process, and additional heating and cooling sources are provided for double-side thermal treatment of the semiconductor workpiece.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device package are disclosed. A method of manufacturing a semiconductor device comprises the steps of testing the semiconductor device using at least a first monitoring pad connected to an internal circuit of the semiconductor device via at least a first fuse circuit; after testing the semiconductor device, electrically disconnecting the first monitoring pad from the internal circuit by opening the first fuse circuit; and after testing of the semiconductor device, electrically connecting at least a first auxiliary pad to the first monitoring pad with at least a first connecting terminal, wherein the first auxiliary pad is connected, through at least a first conductive line, to at least a first power pad of the semiconductor device.

Abstract: The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die.

Abstract: Provided is a manufacturing method for a thermal head, including: bonding a flat upper substrate in a stacked state onto a flat supporting substrate including a heat-insulating concave portion open to one surface thereof so that the heat-insulating concave portion is closed (bonding step (SA2)); thinning the upper substrate bonded onto the supporting substrate by the bonding step (SA2) (plate thinning step (SA3)); measuring a thickness of the upper substrate thinned by the plate thinning step (SA3) (measurement step (SA4)); deciding a target resistance value of heating resistors based on the thickness of the upper substrate, which is measured by the measurement step (SA4) (decision step (SA5)); and forming, at positions of a surface of the upper substrate thinned by the plate thinning step (SA3), the heating resistors having the target resistance value determined by the decision step (SA5), the positions being opposed to the heat-insulating concave portion (resistor forming step (SA6)).

Abstract: A package substrate includes a core board having a through hole; a circuit layer formed on the core board; a metallic ring disposed on the core board surrounding a contour of the through hole, the metallic ring having opening portions positioned opposite to each other, making the metallic ring having a disconnected manner; and an embedded component installed in the through hole. When the embedded component is deviated in the through hole to allow the electrodes to be in contact with the metallic ring, the electrodes are prevented from coming into contact with the same section of the metallic ring to thereby avoid short circuit.

Abstract: Embodiments embed at least one Radio Frequency Identification (RFID) tag into the mold. The mold may comprise a cavity adapted to the geometrical form of the RFID tag. In some embodiments, the cavity is marginally bigger than the RFID tag. In many embodiments, the cavity with the embedded the RFID tag is covered by glue. Thus, the mold, the RFID tag and the glue may be suitable for temperatures up to, e.g., 400° C. Further the mold and the glue may be resistant to concentrated sulfuric acid and formic acid. The serial number of the mold may be stored in the RFID tag. The RFID tag may detect characteristic data during the transfer of the solder from the mold to the wafer. In one embodiment, the RFID tag may detect the temperature. In another embodiment, a plurality of RFID tags may detect various temperatures for controlling the packaging process.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: The present invention relates to the manufacture of a photovoltaic cell panel, said manufacture comprising the steps of: a) obtaining photovoltaic (PV) films that are each intended for a cell and are placed onto a front surface of a metal substrate; b) applying at least one conductive film (CG, CND) onto each front surface of a photovoltaic film; c) cutting up the substrate (SUB) so as to isolate the cells from each other; and d) encapsulating (ENC) the cells on a common mounting. According to the invention, steps d) and c) are reversed, so step d) relates to encapsulating the front surface of the substrate before step c), cutting the substrate up by the rear surface thereof.

Abstract: In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.

Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

Abstract: A semiconductor die is attached onto a substrate on a process platform during manufacturing of a semiconductor package. A dispenser dispenses an adhesive onto the substrate, and the semiconductor die is bonded onto the adhesive which has been dispensed onto the substrate with a bonding tool. Thereafter, a bond line thickness between a bottom surface of the semiconductor die and a top surface of the substrate on the process platform is measured using a measuring device.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.