Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A method includes placing a mold chase over a bottom package, wherein the bottom package has a connector at a top surface of the bottom package. The mold chase includes a cover, and a pin under and connected to the cover. The pin occupies a space extending from a top surface of the connector to the cover. A polymer is filled into a space between the cover of the mold chase and the bottom package. The polymer is then cured. After the step of curing the polymer, the mold chase is removed, and the connector is exposed through an opening in the polymer, wherein the opening is left by the pin of the mold chase.

Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.

Abstract: A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.

Abstract: Provided is a test apparatus for testing a device under test, including a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test, a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package, a testing section that tests the devices under test packaged in the test packages, a removing section that removes the devices under test that have been tested from the test packages, and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages.

Abstract: A chip testing method includes cutting a wafer into chip packages, re-arranging the chip packages on a chip tray, and testing the re-arranged chip packages. The wafer includes a plurality of substrates vertically stacked thereon, and each of the plurality of substrates has a plurality of chips mounted thereon.

Abstract: A light emitting device which is inexpensive and has excellent characteristics and a method for manufacturing the same are provided. In the present invention, a chip-size package including a reflection wall is formed by forming a double structure in which a fluorescent material-containing film piece 2 is bonded on a light extraction surface of a semiconductor light emitting element 6 having bumps 4 and 5 on an electrode-formed surface, and covering an exposed surface of the double structure other than a bump mounting surface 7 and a light exit surface 8 with the reflection wall 3, whereby it is possible to provide a light emitting device which does not need a package substrate, is inexpensive, and has excellent brightness characteristics and heat radiation characteristics, and a manufacturing method having excellent chromaticity yield.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: A method of making a tiled array of semiconductor dies includes aligning and flattening. One end of each semiconductor die has attached thereto a respective printed circuit board. The aligning aligns the semiconductor dies into the tiled array in such a way that the semiconductor dies rest on a vacuum plate and the one end of each die extends beyond an edge of the vacuum plate. The flattening flattens the semiconductor dies against the vacuum plate with a vacuum after the semiconductor dies are aligned.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages (PoPs). The glass via bars can provide high density electrical interconnections in the PoPs. In some implementations, the glass via bars can include integrated passive components. Packaging methods employing glass via bars are also provided.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package.

Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Abstract: A semiconductor module having an integrated structure is manufactured by mounting a semiconductor chip on the side of a surface of a cooling plate via an insulating material, and by molding the semiconductor chip and the cooling plate by a resin-molded member. This method includes the steps of: (a) forming a sprayed insulating film as the insulating material on a surface of the cooling plate; (b) forming a sprayed conductive film on a face of the sprayed insulating film opposite to a face where the cooling plate is provided; (c) checking whether the sprayed conductive film is insulated from the cooling plate by using the sprayed conductive film and the cooling plate as electrodes and applying voltage therebetween; and (d) mounting the semiconductor chip on the upper side of the sprayed conductive film when the sprayed conductive film is insulated, and then resin-molding the semiconductor chip and the cooling plate.

Abstract: To provide a semiconductor device which allows a plurality of semiconductor chips to let a current flow uniformly therethrough and a method of manufacturing the same. The semiconductor device in accordance with one embodiment comprises a plurality of first semiconductor chips and a circuit board, mounted with the plurality of the first semiconductor chips, having first and second wiring conductors electrically connected to the plurality of first semiconductor chips. The plurality of first semiconductor chips are connected in parallel together with the first and second wiring conductors so as to construct a first parallel circuit. The plurality of first semiconductor chips are arranged on the circuit board according to an on-resistance of the plurality of first semiconductor chips so that a uniform current flows through the plurality of first semiconductor chips.

Abstract: Provided is a dicing die-bonding film which is excellent in balance between retention of a semiconductor wafer upon dicing and releasability upon picking up. Disclosed is a dicing die-bonding film comprising a dicing film having a pressure-sensitive adhesive layer on a substrate material, and a die-bonding film formed on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer contains a polymer including an acrylic acid ester as a main monomer, 10 to 40 mol % of a hydroxyl group-containing monomer based on the acrylic acid ester, and 70 to 90 mol % of an isocyanate compound having a radical reactive carbon-carbon double bond based on the hydroxyl group-containing monomer, and is also cured by irradiation with ultraviolet rays under predetermined conditions after film formation on the substrate material, and wherein the die-bonding film contains an epoxy resin, and is also bonded on the pressure-sensitive adhesive layer after irradiation with ultraviolet rays.

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract: A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.

Abstract: An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer.

Abstract: An embodiment is a method. The method comprises providing a substrate comprising a die area. The die area comprises sections of pad patterns, and first sections of the sections each comprise a first uniform pad pattern. The method further comprises probing a first one of the first sections with a first probe card; stepping the first probe card to a second one of the first sections; and probing the second one of the first sections with the first probe card.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A mechanism to electrically evaluate signals within an encapsulated semiconductor device package without the need for redesigning the package substrate is provided. Test bond pads are provided on a top surface of a semiconductor device die being placed within the semiconductor device package. One or more wire bonds having an elevated loop height are formed on the test bond pads. After encapsulating the semiconductor device package, the package encapsulant is subject to a backgrind process to expose a portion of the test connection wire bonds. Only an amount of the package encapsulant sufficient to expose each test connection wire bond is removed, so that the remaining encapsulant will continue to have the same effect on the package as would be present in a production device. Test probes can then be applied to the exposed test connection wire bonds.

Abstract: To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal 15 is being positioned relative to an arrangement direction of a plurality of second contact pins 13a by a positioning pin 13b which a socket 12 includes, a substrate conduction test is performed by bringing a first contact pin 14a into contact with a pre-stack land 5c of a wiring substrate 5 and of the a lower package 2 and moreover bringing the second contact pin 13a into contact with a solder ball 7, and thus the electric inspection can be performed by precisely positioning the first contact pin 14a side and the second contact pin 13a side. Then, the reliability of the electric inspection can be improved.

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: The invention relates to a method for producing a contact for solar cells (30) arranged in a laminated solar panel (1), wherein the solar cells (30) are coated on both sides of the main surfaces thereof with at least one layer and before a lamination step the solar cells (30) are connected with electrically-conducting connectors (31, 33), the electrically conducting connectors (31, 33) being arranged in the solar panel for laminating such as to be completely laminated within the solar panel (1) after the lamination step. After the lamination step a contact region (35) of the electrically-conducting connector (33) is exposed, wherein at least one of the layers covering the solar cells is completely punched through in the corresponding region, in particular by stripping. The contact region (35) of the electrically-conducting connector (33) can then be contacted by means of an externally-accessible contact element.

Abstract: A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.

Abstract: In resin coating, carrying a light-passing member test-coated with a resin on a light-passing member carrying unit; making a light source placed above the light-passing member carrying unit emit excitation light exciting the fluorescent substance; measuring light emission characteristics of the light by irradiating the excitation light emitted from the light source unit from above to the resin coated onto the light-passing member and receiving the light that the resin emits from below the light-passing member by a light emission characteristic measurement unit; obtaining a deviation between a measurement result of the light emission characteristic measurement unit and a prescribed light emission characteristic; and deriving the appropriate resin coating quantity of the resin to be coated onto the LED element as what is used for practical production based on the deviation.

Abstract: System for flash-free overmolding of LED array substrates. In an aspect, a method is provided for molding encapsulations onto an LED array substrate. The method includes attaching a protective tape onto a substrate surface of the substrate so that openings in the protective tape align with LED devices of the substrate and applying molding material onto a molding surface of a molding tool and to portions of the substrate exposed through the openings in the protective tape. The method also includes pressing the molding surface and the substrate surface together at a selected pressure and a selected temperature so that encapsulations are formed on the portions of the substrate exposed through the openings in the protective tape, separating the molding surface from the substrate surface, and removing the protective tape so that molding material flash is removed from the substrate leaving a clean molded substrate.

Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Abstract: The present disclosure provides a light emitting diode (LED) package, which includes a first substrate with electrodes disposed on a top thereof and a second substrate with an LED chip disposed on a top thereof. The LED chip is connected with the electrodes via wires. A first package layer is disposed on the top of the first substrate to cover the wires and electrodes. A fluorescent layer is disposed on the top of the second substrate to cover the LED chip. The present disclosure also provides a mold and a method of manufacturing the LED package.

Abstract: A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.

Abstract: A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of devices. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer to light, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being associated with the predetermined mask pattern and including one or more of the plurality of devices and separating the plurality of semiconductor dies from the carrier substrate.

Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.

Abstract: A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.

Abstract: A method and apparatus (20) for testing the mounting of an integrated circuit (16) on a printed circuit board (12) using a ball grid array comprises measuring the change in height, or drop, of the integrated circuit (16) relative to the printed circuit board (12) following soldering of the ball grid array and comparing the measured drop with a predetermined range. The integrated circuit is deemed to have been successfully mounted to the printed circuit board if the change in height falls within the predetermined range.

Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns.

Abstract: The invention relates to a semiconductor device and a manufacturing method for the same, and makes the rejection rate of the product after chips are stacked and mounted sufficiently low, even when the chips are selected in a conventional, simple and inexpensive wafer test.

Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.

Abstract: The present invention provides a method for manufacturing LED light bar, which includes the following steps: (1) providing light-emitting dies of different sizes; (2) measuring luminous intensities of the light-emitting dies; (3) selecting among the light-emitting diodes ones of which the luminous intensities are different from each other by less than 5%; (4) encapsulating the selected ones of the light-emitting dies to form LED lights, which are of substantially identical encapsulated size; and (5) mounting and electrically connecting the LED lights to a printed circuit board to form an LED light bar. The method for manufacturing LED light bar according to the present invention uses light-emitting dies of different sizes so as to improve utilization rate of an entire wafer and effectively reduce the manufacture cost.

Abstract: A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

Abstract: Embodiments of the present disclosure describe semiconductor substrate techniques and configurations for an optical receiver. In one embodiment, a system includes a semiconductor substrate having one or more optical alignment features formed in a surface of the semiconductor substrate and an optical receiver assembly coupled with the semiconductor substrate, the optical receiver assembly including a photodetector device coupled with the surface of the semiconductor substrate, wherein the one or more optical alignment features facilitate precise optical alignment between a lens assembly and the photodetector device when the lens assembly is coupled with the semiconductor substrate using the one or more optical alignment features. Other embodiments may be described and/or claimed.

Abstract: The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.

Abstract: An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.

Abstract: An ultrasonic probe and an ultrasonic diagnosis device which can improve electrical safety for an operator are provided. The ultrasonic probe 2 has an insulating portion 62 between a mounting board 43 and a case 25. Since electrical leakage from the internal device of the ultrasonic probe 2 can be prevented, electrical safety of the ultrasonic probe 2 for the operator can be improved. A conductive film 61 is provided on the ultrasonic wave radiation side of a cMUT chip 20, and a conductive member 63 is provided along the insulating member 62. A conductive film 61 and a conductive member 63 are connected by a conductive member 64. A closed space having a ground potential is formed by the conductive film 61, the conductive member 63 and a coaxial cable 55 connected to ground. Main components or the body circuits of the ultrasonic probe 2 are contained in the closed space having the ground potential and shielded electrically from the outside.