Introduction Of Nondopant Into Semiconductor Layer Patents (Class 438/162)
  • Patent number: 10243207
    Abstract: Methods for producing nanostructures from copper-based catalysts on porous substrates, particularly silicon nanowires on carbon-based substrates for use as battery active materials, are provided. Related compositions are also described. In addition, novel methods for production of copper-based catalyst particles are provided. Methods for producing nanostructures from catalyst particles that comprise a gold shell and a core that does not include gold are also provided.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 26, 2019
    Assignee: OneD Material LLC
    Inventors: Wanqing Cao, Virginia Robbins, Yimin Zhu
  • Patent number: 9673305
    Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda
  • Patent number: 9595442
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region of a substrate and implanting a second type of dopants in the second region of the substrate. The method includes forming a material layer over the first region and the second region of the substrate and patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure The method includes forming a gate structure across the first fin structure and the second fin structure.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yao Wen, Jui-Yao Lai, Yao-De Chiou, Sai-Hooi Yeong, Yen-Ming Chen
  • Patent number: 9443865
    Abstract: Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are formed in horizontal layers of material above a substrate. A vertically-oriented NAND string is formed in each of the memory holes. Forming the vertically-oriented NAND string channel comprises growing monolithic crystalline silicon upwards in the memory hole from the substrate through all of the plurality of horizontal layers of material. Vapor phase epitaxial growth may be used grow the monolithic crystalline silicon upwards from the bottom of the vertically-oriented NAND channel. Alternatively, a nanowire of monolithic crystalline silicon is synthesized in the memory hole from the substrate at the bottom of the vertically-oriented NAND channel upwards to the top of the vertically-oriented NAND channel.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Peter Rabkin, Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani
  • Patent number: 9425320
    Abstract: Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second electrode and a gate electrode formed on fiber; a channel formed between the first and second electrodes; an encapsulant encapsulating the fiber, the first, second, and gate electrodes, and an upper surface of the channel; and a gate insulating layer formed in a portion of the inner area of the encapsulant.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chwee Iin Choong, Sang-won Kim, Jong-jin Park, Ji-hyun Bae, Jung-kyun Im, Sang-hun Jeon
  • Patent number: 9281358
    Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: March 8, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 9129896
    Abstract: An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Patent number: 9111800
    Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 18, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 9048324
    Abstract: A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×1017 spins/cm3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshiyuki Miyamoto, Masafumi Nomura, Takashi Hamochi, Kenichi Okazaki
  • Patent number: 9029937
    Abstract: A transistor in which the state of an interface between an oxide semiconductor layer and an insulating film in contact with the oxide semiconductor layer is favorable and a method for manufacturing the transistor are provided. Nitrogen is added to the vicinity of the interface between the oxide semiconductor layer and the insulating film (gate insulating layer) in contact with the oxide semiconductor layer so that the state of the interface of the oxide semiconductor layer becomes favorable. Specifically, the oxide semiconductor layer has a concentration gradient of nitrogen, and a region containing much nitrogen is provided at the interface with the gate insulating layer. A region having high crystallinity can be formed in the vicinity of the interface with the oxide semiconductor layer by addition of nitrogen, whereby the interface state can be stable.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9023706
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 9006024
    Abstract: In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 8993386
    Abstract: An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present invention includes the steps of: forming a first conductive layer which functions as a gate electrode over a substrate; forming a first insulating layer to cover the first conductive layer; forming a semiconductor layer over the first insulating layer so that part of the semiconductor layer overlaps with the first conductive layer; forming a second conductive layer to be electrically connected to the semiconductor layer; forming a second insulating layer to cover the semiconductor layer and the second conductive layer; forming a third conductive layer to be electrically connected to the second conductive layer; performing first heat treatment after forming the semiconductor layer and before forming the second insulating layer; and performing second heat treatment after forming the second insulating layer.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Ohara, Toshinari Sasaki
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8963157
    Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: February 24, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Yinan Liang
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8906753
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 9, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8889529
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140302645
    Abstract: Methods of forming a Field Effect Transistor (FET) are provided. The methods may include forming a region that provides enhanced oxidation under a fin-shaped FET (FinFET) body.
    Type: Application
    Filed: April 9, 2013
    Publication date: October 9, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Mark S. Rodder, Kang-ill Seo
  • Patent number: 8828811
    Abstract: A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment and the oxygen doping treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress test (BT test) can be reduced.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8823092
    Abstract: An object is to provide a transistor in which the state of an interface between an oxide semiconductor layer and an insulating film (gate insulating layer) in contact with the oxide semiconductor layer is favorable; and a method for manufacturing the transistor. In order to obtain the transistor, nitrogen is added to a region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer. Specifically, a concentration gradient of nitrogen is formed in the oxide semiconductor layer, and a region containing much nitrogen is provided at the interface with the gate insulating layer. By the addition of nitrogen, a region with high crystallinity can be formed in the region of the oxide semiconductor layer in the vicinity of the interface with the gate insulating layer, so that a stable interface state can be obtained.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8816425
    Abstract: A transistor in which the state of an interface between an oxide semiconductor layer and an insulating film in contact with the oxide semiconductor layer is favorable and a method for manufacturing the transistor are provided. Nitrogen is added to the vicinity of the interface between the oxide semiconductor layer and the insulating film (gate insulating layer) in contact with the oxide semiconductor layer so that the state of the interface of the oxide semiconductor layer becomes favorable. Specifically, the oxide semiconductor layer has a concentration gradient of nitrogen, and a region containing much nitrogen is provided at the interface with the gate insulating layer. A region having high crystallinity can be formed in the vicinity of the interface with the oxide semiconductor layer by addition of nitrogen, whereby the interface state can be stable.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8815660
    Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes a SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qingqing Liang, Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8802515
    Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda
  • Patent number: 8785265
    Abstract: An object to provide a material suitably used for used for a semiconductor included in a transistor, a diode, or the like, with the use of a sputtering method. Specifically, an object is to provide a manufacturing process an oxide semiconductor film having high crystallinity. By intentionally adding nitrogen to the oxide semiconductor, an oxide semiconductor film having a wurtzite crystal structure that is a hexagonal crystal structure is formed. In the oxide semiconductor film, the crystallinity of a region containing nitrogen is higher than that of a region hardly containing nitrogen or a region to which nitrogen is not intentionally added. The oxide semiconductor film having high crystallinity and having a wurtzite crystal structure is used as a channel formation region of a transistor.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8748243
    Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8728883
    Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8704229
    Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Peter Javorka, Glyn Braithwaite
  • Patent number: 8679905
    Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 25, 2014
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20140042539
    Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
    Type: Application
    Filed: August 6, 2013
    Publication date: February 13, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Chi Sun HWANG, Sang Hee PARK, Him Chan OH
  • Patent number: 8629496
    Abstract: An object to provide a material suitably used for used for a semiconductor included in a transistor, a diode, or the like, with the use of a sputtering method. Specifically, an object is to provide a manufacturing process an oxide semiconductor film having high crystallinity. By intentionally adding nitrogen to the oxide semiconductor, an oxide semiconductor film having a wurtzite crystal structure that is a hexagonal crystal structure is formed. In the oxide semiconductor film, the crystallinity of a region containing nitrogen is higher than that of a region hardly containing nitrogen or a region to which nitrogen is not intentionally added. The oxide semiconductor film having high crystallinity and having a wurtzite crystal structure is used as a channel formation region of a transistor.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8569159
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 8563399
    Abstract: The invention relates to a detachable substrate for the electronics, optics or optoelectronics industry, that includes a detachable layer resting on a buried weakened region. This substrate is remarkable in that this buried weakened region consists of a semiconductor material that is denser in the liquid state than in the solid state and that contains in places precipitates of naturally volatile impurities. The invention also relates to a process for fabricating and detaching a detachable substrate.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 22, 2013
    Assignee: Soitec
    Inventor: Michel Bruel
  • Patent number: 8530290
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-hoon Yang, Jin-Wook Seo, Sei-Hwan Jung, Ki-Yong Lee
  • Patent number: 8513072
    Abstract: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Ikuko Kawamata
  • Patent number: 8476124
    Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: July 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Junji Oh
  • Patent number: 8440484
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 8421173
    Abstract: A chip package structure includes a silicon substrate, a sensing component, a metal circuit layer, a first insulating layer and a conductive metal layer. The silicon substrate has opposite first and second surfaces. The sensing component is disposed on the first surface. The metal circuit layer is disposed on the first surface and electrically connected to the sensing component. The first insulating layer covers the second surface and has a first through hole to expose a portion of the second surface. The conductive metal layer is disposed on the first insulating layer and includes first leads and a second lead. The first leads are electrically connected to the metal circuit layer. The second lead is filled in the first through hole to electrically connect to the silicon substrate and one of the first leads. A chip packaging process for fabricating the chip package structure is also provided.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 16, 2013
    Assignee: Pixart Imaging Inc.
    Inventors: Wei-Chung Wang, Sen-Huang Huang
  • Patent number: 8420462
    Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Kobayashi, Ikuko Kawamata
  • Patent number: 8338240
    Abstract: To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Shinobu Furukawa
  • Patent number: 8338277
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 25, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8318551
    Abstract: A gate electrode layer over a substrate; a gate insulating layer over the gate electrode layer; a first source electrode layer and a first drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and a second source electrode layer and a second drain electrode layer over the oxide semiconductor layer. A first part, a second part, and a third part of a bottom surface are in contact with the first source electrode layer, the first drain electrode layer, and the gate insulating layer respectively. A first part and a second part of the top surface are in contact with the second source electrode layer and the second drain electrode layer respectively. The first source electrode layer and the first drain electrode layer are electrically connected to the second source electrode layer and the second drain electrode layer respectively.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki
  • Patent number: 8293626
    Abstract: It is an object to provide a homogeneous semiconductor film in which variation in the size of crystal grains is reduced. Alternatively, it is an object to provide a homogeneous semiconductor film and to achieve cost reduction. By introducing a glass substrate over which an amorphous semiconductor film is formed into a treatment atmosphere set at more than or equal to a temperature that is needed for crystallization, rapid heating due to heat conduction from the treatment atmosphere is performed so that the amorphous semiconductor film is crystallized. More specifically, for example, after the temperature of the treatment atmosphere is increased in advance to a temperature that is needed for crystallization, the substrate over which the semiconductor film is formed is put into the treatment atmosphere.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Naoki Okuno
  • Patent number: 8293595
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 8250153
    Abstract: An electronic mail (email) system may include at least one email server having mailboxes for storing email messages, and a plurality of mobile wireless communications devices. The system may further include at least one email aggregation server for repetitively polling the mailboxes for email messages, and forwarding the email messages to respective mobile wireless communications devices. The at least one email aggregation server may determine time overlapped polling of corresponding mailboxes and time stagger a next polling thereof.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: August 21, 2012
    Assignee: Research In Motion Limited
    Inventor: Harshad N. Kamat
  • Patent number: 8211786
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Publication number: 20120083079
    Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.
    Type: Application
    Filed: July 5, 2011
    Publication date: April 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Junji Oh
  • Patent number: 8133771
    Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Kobayashi, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
  • Patent number: 8114726
    Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: February 14, 2012
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Toshiharu Marui, Hideyuki Okita
  • Patent number: 8101522
    Abstract: A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nanostructures.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: January 24, 2012
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Shu-Jia Syu