Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.

Abstract: The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.

Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

Abstract: A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nanostructures.

Abstract: A laser annealing method includes forming a nitrogen-doped layer on a semiconductor layer, the nitrogen-doped layer having a nitrogen concentration of at least 3×1020 atoms/cc, irradiating a first area of the nitrogen-doped layer in a low oxygen environment with a laser beam and irradiating a second area of the nitrogen-doped layer in a low oxygen environment with a laser beam, a part of the second area overlapping with the first area.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: A method of synthesizing silicon wires is provided. A substrate is provided. A copper catalyst particle layer is formed on a top surface of the substrate. The reactive device is heated at a temperature of above 450° C. in a flowing protective gas. A mixture of a protective gas and a silicon-based reactive gas is introduced at a temperature above 450° C. at a pressure below 700 Torr to form the silicon wires on the substrate.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.

Abstract: Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.

Abstract: A method of fabricating a pixel structure is provided. A gate electrode is formed on a substrate, and a dielectric layer is formed on the gate electrode. A patterned metal oxide semiconductor layer and a patterned metallic etching stop layer are formed on the dielectric layer above the gate electrode. A first conductive layer is formed to cover the patterned metallic etching stop layer and the dielectric layer. The first conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a source and a drain. A second conductive layer is formed to cover the source, the drain and the dielectric layer. The second conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a first electrode layer. The patterned metallic etching stop layer exposed between the source and the drain is removed.

Abstract: The method for forming first and second metal-based materials comprises providing a substrate comprising an area made from a first semi-conductor material and an area made from a second semi-conductor material comprising germanium separated by a pattern made from dielectric material, depositing a metal layer and performing a first heat treatment in an atmosphere comprising a quantity of oxygen comprised between 0.01% and 5%. The metal layer reacts with the first semi-conductor material and the second semi-conductor material comprising germanium to respectively form the first metal-based material and the second metal-based material containing germanium.

Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate 9, e.g., a monosilane gas, in a vacuum chamber 1. Thus, the inner wall of the vacuum chamber 1 is covered with a silicon-containing film. Then, a plasma doping process is performed on the silicon substrate 9.

Abstract: Circuit board having conductor wiring and connection terminal; anisotropic conductive resin layer provided on one surface of circuit board; and plurality of electronic components respectively provided with electrode terminals in positions facing the connection terminal are included. The anisotropic conductive resin layer includes at least one kind of conductive particles selected from coiled conductive particles, fiber fluff conductive particles and conductive particles provided with a plurality of conductive protrusions, and resin binder; electrically couples electrode terminals of plurality of electronic components to connection terminals to each other with conductive particles; mechanically fixes electronic components and circuit board to each other; and protects conductor wiring.

Abstract: A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a metal catalyst doped into the amorphous silicon thin film are optimized to reduce the regions of a metal silicide distributed at grain boundaries of the polycrystalline silicon thin film. In addition, oxygen (O2) gas or water (H2O) vapor is supplied to form a passivation film on the surface of the polycrystalline silicon thin film.

Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

Abstract: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

Abstract: The present invention provides a production method of a semiconductor device, which can improve characteristics of a semiconductor element including a single crystal semiconductor layer formed by transferring on an insulating substrate. The present invention is a production method of a semiconductor device comprising a single crystal semiconductor layer formed on an insulating substrate, the production method comprising the steps of: implanting a substance for separation into a single crystal semiconductor substrate, thereby forming a separation layer; transferring a part of the single crystal semiconductor substrate, separated at the separation layer, onto the insulating substrate, thereby forming the single crystal semiconductor layer; forming a hydrogen-containing layer on at least one side of the single crystal semiconductor layer; and diffusing hydrogen from the hydrogen-containing layer to the single crystal semiconductor layer.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.

Abstract: A method for manufacturing a semiconductor device and a display device each including a thin film transistor which has excellent electric characteristics and high reliability, with high mass productivity. In a display device which includes a channel-etch inversely-staggered thin film transistor in which a microcrystalline semiconductor layer is used for a channel formation region, the microcrystalline semiconductor layer is formed of a stacked layer of a microcrystalline semiconductor film which is formed by a deposition method and can be a nucleus of crystal growth and an amorphous semiconductor film; a conductive film and a semiconductor film which forms a source region and a drain region and to which an impurity imparting one conductivity is added are formed over the amorphous semiconductor film; and the conductive film is irradiated with laser light.

Abstract: After a gate oxide film 10 has been formed on a silicon substrate G, a first step of forming a microcrystalline silicon film by high electron density plasma of an electron temperature of 2.0 eV or less and a second step of forming an ultra-microcrystalline silicon film by high electron density plasma of an electron temperature higher than 2.0 eV are repeated. A stacked-layer film 20 of the ultra-microcrystalline silicon film and the microcrystalline silicon film is thereby formed. With the film formation method described above, at least one of an n-channel thin-film transistor and a p-channel thin-film transistor with the stacked-layer film 20 functioned as an active layer may be manufactured.

Abstract: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the micro-cavities, and the semiconductor element is formed using the doping atoms.

Abstract: A method of fabricating a CMOS thin film transistor includes: providing a substrate; forming an amorphous silicon layer on the substrate; performing a first annealing process on the substrate and crystallizing the amorphous silicon layer into a polysilicon layer; patterning the polysilicon layer to form first and second semiconductor layers; implanting first impurities into the first and second semiconductor layers; implanting second impurities into the first or second semiconductor layer; and performing a second annealing process on the semiconductor layers to remove the metal catalyst remaining in the first or second semiconductor layer, on which the second impurities are implanted, wherein the first impurities are implanted at a dose of 6×1013/cm2 to 5×1015/cm2, and the second impurities are implanted at a dose of 1×1011/cm2 to 3×1015/cm2.

Abstract: To provide a method for producing a high-performance semiconductor device by a simple and low-temperature process. The method for producing a semiconductor device, in accordance with the present invention, is a production method of a semiconductor device including a first insulating film, a semiconductor layer, and a second insulating film in this order on a substrate, the method including the steps of: forming a first insulating film including a hydrogen barrier layer; forming a semiconductor layer on a region where the hydrogen barrier layer of the first insulating film is formed; injecting hydrogen into the semiconductor layer; forming a second insulating film, the second insulating film including a hydrogen barrier layer on at least a region where the semiconductor layer is formed; and subjecting the semiconductor layer to hydrogenation annealing.

Abstract: A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region.

Abstract: This patent relates to a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an insulating layer formed in a semiconductor substrate, trenches formed within the insulating layer, silicon layers formed within the trenches, gates formed on the silicon layers, and junctions formed in the silicon layers at both sides of the gates.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: A method of fabricating a semiconductor device includes forming an ion implanted region on a semiconductor substrate in a cell/core region. The semiconductor substrate is selectively etched to form a recess. The recess exposes a boundary of the ion implanted region. The ion implanted region exposed at the bottom of the recess is removed to form an under-cut space in the semiconductor substrate. An insulating film is formed to form a substrate having a silicon-on-insulator (SOI) structure in the cell/core region. The insulating film fills the under-cut space and the recess.

Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities and carbide precipitates in the substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, annealing the substrate such that at least a part of the crystallographic defects are eliminated using the micro-cavities and the carbide precipitates, and wherein the semiconductor element is formed using the doping atoms.

Abstract: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions are kept within a predetermined range. A laser beam having a wave length region, which can give more energy to the amorphous region than to the crystal region, is irradiated to the first polycrystalline semiconductor film, it is possible to crystallize the amorphous region without destroying the crystal region. If a TFT is manufactured based on a second polycrystalline semiconductor film, which is obtained through the above-mentioned crystallization processes, the TFT with high electric characteristics and less fluctuation can be obtained.

Abstract: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According to the present invention, it is characterized in that, after laser beam crystallization on the semiconductor film, heat treatment is carried out so as to reduce the warp in the film. Since the substrate contracts by the heat treatment, the warp in the semiconductor film is lessened, so that the physical properties of the semiconductor film can be improved.

Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.

Abstract: A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.

Abstract: The present invention relates to a method of manufacturing a semiconductor substrate, which enables a semiconductor device to have high speed operating characteristics and high performance characteristics such as lower electrical power consumption, and a method of manufacturing a semiconductor device including a method of manufacturing the semiconductor substrate thereof in a process, as well as to a semiconductor substrate manufactured by the method of manufacturing the same and a semiconductor device manufactured using the semiconductor substrate.

Abstract: A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Abstract: The present invention relates to a method for manufacturing a semiconductor film, including the steps of forming a transparent conductive film, forming a first conductive film over the transparent conductive film, forming a second conductive film over the first conductive film, etching the second conductive film with a gas including chlorine, and etching the first conductive film with a gas including fluorine. During etching of the second conductive film with a gas including chlorine, the transparent conductive film is protected by the first conductive film. During etching of the first conductive film with the gas including fluorine, the transparent conductive film does not react with the gas including fluorine. Therefore, no particle is formed.

Abstract: Upon manufacture of a semiconductor device provided with a source region and a drain region formed by activating, through anneal, an n-type first dopant ion-implanted in a p-type device forming area provided in a semiconductor layer formed on an insulator, and a body region, (a) ion implantation of Ar in a boundary region between the source and drain regions to be formed, which corresponds to a region lying in a predeterminate area for forming the body region, and (b) high-temperature anneal for partly recovering crystal defects produced by the ion implantation of the Ar at a temperature higher than the anneal for activation of the first dopant are carried out prior to the ion-implantation of the first dopant.

Abstract: Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains in a semiconductor film obtained using the metallic element. With the technique of the present invention, to remove a catalytic element used to crystallize a semiconductor film having an amorphous structure, gettering is completed by forming a region or a semiconductor film, to which a rare gas element is added, and by having the catalytic element move to the formed region or semiconductor film.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A method of forming a surface Ge-containing channel which can be used to fabricate a Ge-based field effect transistor (FET) which can be applied to semiconductor-on-insulator substrates (SOIs) is provided. The disclosed method uses Ge-containing ion beams, such as cluster ion beams, to create a strained Ge-containing rich region at or near a surface of a SOI substrate. The Ge-containing rich region can be present continuously across the entire surface of the semiconductor substrate, or it can be present as a discrete region at a predetermined surface portion of the semiconductor substrate.

Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

Abstract: A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on a semiconductor film having a crystal structure by plasma CVD from monosilane and nitrous oxide as material gas. In a step of forming a gettering site, a semiconductor film having an amorphous structure and containing a high concentration of noble gas element, specifically, 1×1020 to 1×1021/cm3, is formed by plasma CVD. The film is typically an amorphous silicon film. Then gettering is conducted.