Introduction Of Nondopant Into Semiconductor Layer Patents (Class 438/162)
  • Patent number: 7439092
    Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 21, 2008
    Assignee: Commissariat A l'Energie Atomique
    Inventor: Aurélie Tauzin
  • Patent number: 7435635
    Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm?3 or lower, preferably 1×1019 atoms·cm?3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: October 14, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Naoto Kusumoto, Yasuhiko Takemura
  • Patent number: 7432139
    Abstract: A method for forming a semiconductor structure, the method including forming in a processing chamber a dielectric layer over a substrate; and subsequently forming, in the same processing chamber and without removing the substrate therefrom, an electrode layer directly over and in contact with the dielectric layer.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: October 7, 2008
    Assignee: AmberWave Systems Corp.
    Inventor: Matthew T. Currie
  • Publication number: 20080157094
    Abstract: A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, including a source region, a drain region and a channel region, and made of a polycrystalline silicon layer; a gate electrode disposed to correspond to the channel region of the semiconductor layer; a gate insulating layer disposed between the semiconductor layer and the gate electrode; and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer, respectively, wherein the polycrystalline silicon layer comprises a plurality of regions having different Raman spectrum peaks from each other.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 3, 2008
    Applicant: Samsung SDI Co., Ltd.
    Inventors: JIN-WOOK SEO, Byoung-Keon Park, Tae-Hoon Yang, Ki-Yong Lee
  • Publication number: 20080135873
    Abstract: Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 12, 2008
    Applicant: AmberWave Systems Corporation
    Inventors: James Fiorenza, Mark Carroll, Anthony J. Lochtefeld
  • Publication number: 20080105871
    Abstract: An exemplary thin film transistor (TFT) array substrate (200) includes: a substrate (210), a gate electrode (220) disposed on the substrate, a gate insulating layer (230) disposed on the substrate having the gate electrode, a lightly doped amorphous silicon (a-Si) layer (241) disposed on the gate insulating layer, a first a-Si layer (242) disposed on the lightly doped a-Si layer, a source electrode (251) and a drain electrode (252) disposed on the gate insulating layer and the a-Si layer. The thin film transistor array substrate has a low leakage current.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 8, 2008
    Inventors: Shuo-Ting Yan, Chien-Hsiung Chang, Yu-Hsiung Chang, Kai-Yuan Cheng, Tsau-Hua Hsieh, Chao-Yi Hung, Chao-Chih Lai
  • Patent number: 7368751
    Abstract: A method of manufacturing an electronic device comprising a thin film transistor (42), comprises forming a hydrogen-containing layer (22) over a semiconductor layer (10;20), irradiating the hydrogen-containing layer so as to hydrogenate the semiconductor layer, and then forming electrodes (24;26,28) over the semiconductor layer. A short diffusion length and direct path is provided for the hydrogen thus allowing rapid hydrogenation of the semiconductor layer using relatively few, high-fluence laser pulses. The supporting substrate (12) is not heated significantly making the method particularly useful for TFTs on polymer substrates. Crystallisation and hydrogenation of the semiconductor layer can be executed in the same irradiation step.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 6, 2008
    Assignee: TPO Hong Kong Holding Limited
    Inventors: Nigel D. Young, Soo Y. Yoon, Ian D. French, David J. McCulloch
  • Patent number: 7348222
    Abstract: It is an object of the present invention to provide a method for removing the metal element from the semiconductor film which is different from the conventional gettering step for removing the metal element from the semiconductor film. In the present invention, when Ni element (Ni) is used as the metal element and a silicon-based film (referred to as a silicon film) is used as the semiconductor film, nickel silicide segregates in the ridge formed in the silicon film by irradiating the pulsed laser light. Next, etching solution of hydrofluoric acid based etchant is used to remove the nickel silicide segregated in the ridge. When the surface of the semiconductor film is rough after removing the metal element by means of etching, the laser light may be irradiated to the semiconductor film under the insert atmosphere to flatten the surface thereof.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 25, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hideto Ohnuma, Hironobu Shoji
  • Patent number: 7332443
    Abstract: The present invention relates to a method for fabricating a semiconductor device. In order to provide for a high carrier mobility in an active region of the device, germanium atoms are implanted into a surface of a semiconductor substrate such that a germanium-containing layer inside the semiconductor substrate is formed. Then, the surface of the semiconductor surface is oxidized down to and including the upper part of the germanium-containing layer, thereby pushing the implanted germanium atoms from the surface down into the semiconductor substrate and thereby enhancing the germanium concentration inside the remaining germanium-containing layer and forming a layer with enhanced germanium concentration inside the semiconductor substrate. The fabrication of the semiconductor device is concluded such that the active region of the device is placed at least partly within the layer with enhanced germanium concentration.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 19, 2008
    Assignee: Infineon Technologies AG
    Inventor: Ralph Stoemmer
  • Patent number: 7320921
    Abstract: A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: January 22, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ta-Wei Wang
  • Patent number: 7288444
    Abstract: A method of manufacturing a thin film transistor that provides high electric field mobility is disclosed.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: October 30, 2007
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Woo-Young So
  • Patent number: 7265002
    Abstract: A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 4, 2007
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20070166899
    Abstract: A method of synthesizing silicon wires generally includes the steps of: providing a substrate; forming a copper catalyst particle layer on a top surface of the substrate; heating the reactive device at a temperature of above 450° C. in a flowing protective gas; and introducing a mixture of a protective gas and a silicon-based reactive gas at a temperature of above 450° C. at a pressure of below 700 Torr, thereby forming the silicon wires on the substrate.
    Type: Application
    Filed: September 22, 2006
    Publication date: July 19, 2007
    Applicants: Tsinghua University, HON HAI Precision Industry CO., LTD.
    Inventors: Yuan Yao, Li-Guo Xu, Shou-Shan Fan
  • Publication number: 20070161167
    Abstract: Non-uniformity of the sheet resistance associated with ion implantation into a polysilicon semiconductor layer using a ribbon-shaped beam is minimized to prevent variations in the characteristics of fabricated thin film transistors. When the implanted ions are of a first element, a second element that is heavy and has no influence on electric charge is implanted at a critical implantation quantity or more into a dose region of the polysilicon semiconductor layer into which the ions of the first element are implanted.
    Type: Application
    Filed: November 17, 2006
    Publication date: July 12, 2007
    Inventors: Jun Gotoh, Akio Kawano
  • Patent number: 7226820
    Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 5, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Jing Liu, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
  • Patent number: 7226823
    Abstract: In a method of obtaining a crystalline silicon film having high crystallinity at a low temperature and for a short time by using a catalytic element and using both a heat treatment and irradiation of laser light, a catalytic element which does not require a gettering step is used as the catalytic element for facilitating crystallization, so that a semiconductor device having high characteristics and high productivity is obtained. Specifically, a coating film of an element in group 14, such as germanium, which is the same group of the periodic table as silicon is formed on an amorphous silicon film formed on a glass substrate, a heat treatment at 550° C. for 4 hours is carried out, and further, irradiation of laser light is carried out, so that a crystalline silicon film is obtained.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Shunpei Yamazaki
  • Patent number: 7211961
    Abstract: There is provided a method of easily forming thin film transistors having the same characteristics in fabricating a differential circuit or a current mirror circuit utilizing two thin film transistors made of a polycrystalline silicon semiconductor. Four each thin film transistors are used in a differential circuit and a current mirror circuit, respectively. The thin film transistors are arranged to be symmetric to each other about a symmetry center instead of using thin film transistors arranged adjacently on the substrate in the respective circuits.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: May 1, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 7202119
    Abstract: An orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film is increased, a distortion thereof is suppressed, and a TFT using such a crystalline semiconductor film is provided. At the time of formation of the amorphous semiconductor film (102) or after the formation thereof, a noble gas element, typically, argon is included in the film and crystallization is performed therefor. Thus, an orientation ratio of the semiconductor film (104) can be increased and a distortion present in the semiconductor film (104) after the crystallization is suppressed as compared with that present in the semiconductor film before the crystallization. Then, the noble gas element in the film is removed or reduced by laser light irradiation performed later.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki
  • Patent number: 7192817
    Abstract: A method for manufacturing a semiconductor device including forming a gate electrode over a substrate; forming a pate insulating film over the pate electrode and over the substrate; forming a semiconductor film on the gate insulating film; providing the semiconductor film with a metal element; crystallizing the semiconductor film provided with the metal element; doping an element which is used for gettering into a portion of the crystallized semiconductor film; and heating the crystallized semiconductor film whereby the metal element contained in a channel region of the semiconductor film is gettered by the portion.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: March 20, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoaki Yamaguchi, Setsuo Nakajima
  • Patent number: 7186597
    Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 6, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 7183145
    Abstract: In a crystallization process of an amorphous semiconductor film, a first polycrystalline semiconductor film, in which amorphous regions are dotted within the continuous crystal region, is obtained by performing heat treatment after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. At this point, the amorphous regions are kept within a predetermined range. A laser beam having a wave length region, which can give more energy to the amorphous region than to the crystal region, is irradiated to the first polycrystalline semiconductor film, it is possible to crystallize the amorphous region without destroying the crystal region. If a TFT is manufactured based on a second polycrystalline semiconductor film, which is obtained through the above-mentioned crystallization processes, the TFT with high electric characteristics and less fluctuation can be obtained.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: February 27, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hideto Ohnuma, Chiho Kokubo
  • Patent number: 7160784
    Abstract: When a laser beam is irradiated onto a semiconductor film, a steep temperature gradient is produced between a substrate and the semiconductor film. For this reason, the semiconductor film contracts, so that a warp in the film occurs. Therefore, the quality of a resulting crystalline semiconductor film sometimes deteriorates. According to the present invention, it is characterized in that, after laser beam crystallization on the semiconductor film, heat treatment is carried out so as to reduce the warp in the film. Since the substrate contracts by the heat treatment, the warp in the semiconductor film is lessened, so that the physical properties of the semiconductor film can be improved.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: January 9, 2007
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Tamae Takano
  • Patent number: 7129533
    Abstract: A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark A. Armstrong, Stephen M. Cea, Giuseppe Curello, Sing-Chung Hu, Aaron D. Lilak, Max Wei
  • Patent number: 7122452
    Abstract: A method of producing a semiconductor device on a silicon on insulator (SOI) substrate is disclosed. In one aspect, the method comprises providing a device with a monocrystalline semiconductor layer on an insulating layer; providing a mask on the semiconductor layer to provide first shielded portions and first unshielded portions, amorphizing the first unshielded portions to yield first amorphized portions of the monocrystalline semiconductor layer, implanting a first dopant in the first amorphized portions, applying a first solid phase epitaxial regrowth action to the semiconductor device while using the first shielded portions as monocrystalline seeds.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 17, 2006
    Assignees: Interuniversitair Microelektronica Centrum (IMEC) vzw, Koninklijke Philips Electronics
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 7115453
    Abstract: Provided is a technique of effectively removing a metallic element that has catalytic action in terms of the crystallization of a semiconductor film and remains in a semiconductor film obtained using the metallic element. With the technique of the present invention, to remove a catalytic element used to crystallize a semiconductor film having an amorphous structure, gettering is completed by forming a region or a semiconductor film, to which a rare gas element is added, and by having the catalytic element move to the formed region or semiconductor film.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: October 3, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Masayuki Kajiwara, Shunpei Yamazaki, Hideto Ohnuma
  • Patent number: 7115452
    Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large getting capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: October 3, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Hisashi Ohtani
  • Patent number: 7109074
    Abstract: A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on a semiconductor film having a crystal structure by plasma CVD from monosilane and nitrous oxide as material gas. In a step of forming a gettering site, a semiconductor film having an amorphous structure and containing a high concentration of noble gas element, specifically, 1×1020 to 1×1021/cm3, is formed by plasma CVD. The film is typically an amorphous silicon film. Then gettering is conducted.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: September 19, 2006
    Assignee: Semiconductor Engery Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Taketomi Asami, Noriyoshi Suzuki
  • Patent number: 7094663
    Abstract: The semiconductor device has a low-resistance layer provided under the interconnection extending from the signal input to a gate of MOSFET. The low-resistance layer decreases the substrate resistance and the noise characteristic of the semiconductor device can also be improved. The low-resistance layer can be provided on a surface of the substrate or a polysilicon interconnection.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Morifuji
  • Patent number: 7084017
    Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: August 1, 2006
    Assignee: Advanced Display Inc.
    Inventors: Nobuhiro Nakamura, Kazunori Inoue, Takuji Yoshida, Kazuhiro Kobayashi, Ken Nakashima
  • Patent number: 7071119
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: July 4, 2006
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Patent number: 7060544
    Abstract: A fabricating method of a thin film transistor includes forming an active layer of polycrystalline silicon, forming a first insulating layer on the active layer, forming a gate electrode on the first insulating layer over the active layer, doping side portions of the active layer with impurities, applying a small amount of metal to the side portions of the active layer and activating the side portions of the active layer such that the small amount of metal is adsorbed into the active layer.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: June 13, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Hae-Yeol Kim, Jong-Uk Bae, Binn Kim
  • Patent number: 7052942
    Abstract: The present invention relates to passivation of a gallium nitride (GaN) structure before the GaN structure is removed from an epitaxial growth chamber. The GaN structure includes one or more structural epitaxial layers deposited on a substrate, and the passivation layer deposited on the structural epitaxial layers. In general, the passivation layer is a dielectric material deposited on the GaN structure that serves to passivate surface traps on the surface of the structural epitaxial layers. Preferably, the passivation layer is a dense, thermally deposited silicon nitride passivation layer.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: May 30, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Joseph Smart, David Grider, Shawn Gibb, Brook Hosse, Jeffrey Shealy
  • Patent number: 7049183
    Abstract: A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: May 23, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Michinori Iwai, Shinya Morino, Takayuki Tsutsumi
  • Patent number: 7045818
    Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 16, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yushi Jinno, Shiro Nakanishi, Kyoko Hirai, Tsutomu Yamada, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 7033871
    Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: April 25, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Shunpei Yamazaki, Koji Dairiki, Masayuki Kajiwara, Junichi Koezuka, Satoshi Murakami
  • Patent number: 7033902
    Abstract: A method for making a thin film transistor (TFT) with a lightly doped region. The process of the invention is compatible with the currently common TFT manufacturing processes. A substrate with a photoresist layer thereon is subjected to two-step exposure with different exposure energies to form a full-through pattern and a non-through pattern after development. The same photoresist layer is subjected to two etching steps to form a gate region and an intra-gate region. The gate region and the intra-gate region are respectively doped with different dopant concentrations. Therefore, the number of times forming and exposing the photoresist layer is reduced.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: April 25, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Shih-Chang Chang, De-Hua Deng, Yaw-Ming Tsai
  • Patent number: 7026197
    Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: April 11, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Hisashi Ohtani
  • Patent number: 7009205
    Abstract: An image display device using transistors each having a polycrystalline semiconductor layer constructed so that drain and source regions are fully activated, and a manufacturing method thereof. The polycrystalline semiconductor layer is so provided that impurity concentrations are easy to control in LDD regions . The image display device further uses transistors having a gate electrode on an upper surface of the semiconductor layer with an insulating film therebetween, a drain region formed on one side of the gate electrode, and a source region formed on another side of the gate electrode. An activated P-type impurity is added to the area underlying the gate electrode, and an activated N-type impurity is added to the area excluding the area underlying the gate electrode.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: March 7, 2006
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Jun Gotoh, Katsutoshi Saito, Makoto Ohkura, Yukio Takasaki, Masanao Yamamoto
  • Patent number: 7005362
    Abstract: A method of fabricating a TFT includes a step of forming an impurity region for a source and a drain by simultaneously implanting and activating impurity ions. More particularly, the present invention includes the steps of forming a gate insulating layer and a gate on a predetermined and selected portion of an active layer, forming an excited region in the exposed portion of the active layer by implanting hydrogen ions to the active layer by using the gate as a mask, and forming an impurity region by implanting impurity ions heavily to the excited region which remains in an excited state.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: February 28, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Joon-Young Yang
  • Patent number: 6955953
    Abstract: A method of manufacturing a semiconductor with a storage capacitor having sufficient memory capacity while requiring a minimum area is provided. The method includes steps for manufacturing a storage capacitor of a pixel region that has a structure of a first storage capacitor and a second storage capacitor stacked on top of the other and connected in parallel with each other. The method further includes steps for forming the first storage capacitor having a first capacitance electrode formed in the same layer as a drain region, a first dielectric, and a second capacitance electrode formed in the same layer as a gate wiring. Still further, the method includes steps for forming the second storage capacitor including the second capacitance electrode, a second dielectric, and a third capacitance electrode formed in the same layer as a light-shielding film.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: October 18, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda, Takeshi Fukunaga
  • Patent number: 6953714
    Abstract: A method for producing a thin film semiconductor device is described. In the method, a thin film layer of non-single-crystalline semiconductor, which is deposited on a base layer of glass, is processed to an island-shaped thin film layer at the time prior to the layer irradiation step. The laser irradiation to the thin film layer of non-single-crystalline semiconductor is carried out after forming an insulation film layer and a gate electrode over the island-shaped thin film layer, by using the gate electrode as the irradiation mask, whereby the center area of the island-shaped thin film layer masked by the gate electrode is crystallized, and simultaneously, the both side areas thereof which is not masked by the gate electrode are annealed. Next, a source electrode and a drain electrode is formed in the annealed areas. The implantation of impurity ion may be carried out either before or after the laser irradiation.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: October 11, 2005
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yoshinobu Kimura, Masakiyo Matsumura, Mikihiko Nishitani, Masato Hiramatsu, Masayuki Jyumonji, Yoshitaka Yamamoto, Hideo Koseki
  • Patent number: 6949418
    Abstract: A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 27, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 6949796
    Abstract: A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed between third and fourth semiconductor regions. The method comprises the steps of, in turn, halo-implanting each of the first, second, third, and fourth semiconductor regions, with the other three semiconductor regions being masked, in a projected direction which (i) is essentially perpendicular to the direction of the respective gate region and (ii) points from the halo-implanted semiconductor region to the respective gate region.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Kirk D. Peterson, Jeffrey S. Zimmerman
  • Patent number: 6939754
    Abstract: A high-quality isotropic polycrystalline silicon (poly-Si) and a method for fabricating high quality isotropic poly-Si film are provided. The method includes forming a film of amorphous silicon (a-Si) and using a MISPC process to form poly-Si film in a first area of the a-Si film. The method then anneals a second area, included in the first area, using a Laser-Induced Lateral Growth (LILaC) process. In some aspects, a 2N-shot laser irradiation process is used as the LILaC process. In some aspects, a directional solidification process is used as the LILaC process. In response to using the MISPC film as a precursor film, the method forms low angle grain boundaries in poly-Si in the second area.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 6, 2005
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Masao Moriguchi, Apostolos T. Voutsas, Mark A. Crowder
  • Patent number: 6927107
    Abstract: In a production method of a semiconductor device, a catalyst element, e.g. Ni, is added to an amorphous silicon film, formed on a substrate with an insulating surface, for promoting crystallization of the amorphous silicon film. Thereafter, the amorphous silicon film is subjected to heat treatment to cause crystal growth therein. Next, the crystal growth is stopped in a state where minute amorphous regions (uncrystallized regions) remain in the film. Next, the silicon film is irradiated with strong light (laser light) so as to be further crystallized. As a result, a crystalline silicon film that has high quality and is excellent in uniformity is obtained.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: August 9, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoki Makita, Hiromi Sakamoto, Masao Moriguchi
  • Patent number: 6916693
    Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: July 12, 2005
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hideto Ohnuma, Chiho Kokubo, Koichiro Tanaka, Naoki Makita, Shuhei Tsuchimoto
  • Patent number: 6913956
    Abstract: The present invention is characterized in that a semiconductor film containing a rare gas element is formed on a crystalline semiconductor film obtained by using a catalytic element via a barrier layer, and the catalytic element is moved from the crystalline semiconductor film to the semiconductor film containing a rare gas element by a heat treatment. Furthermore, a first impurity region and a second impurity region formed in a semiconductor layer of a first n-channel TFT are provided outside a gate electrode. A third impurity region formed in a semiconductor layer of a second n-channel TFT is provided so as to be partially overlapped with a gate electrode. A third impurity region is provided outside a gate electrode. A fourth impurity region formed in a semiconductor layer of a p-channel TFT is provided so as to be partially overlapped with a gate electrode. A fifth impurity region is provided outside a gate electrode.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: July 5, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Hamada, Satoshi Murakami, Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka, Toru Takayama
  • Patent number: 6908780
    Abstract: A laser repair facilitated pixel structure and repair method. The pixel structure includes a thin film transistor, a pixel electrode, and a conductive line. Control of the pixel structure is carried out through signals passing to a scan line and a data distributing line. The conductive line is underneath the data distributing line. The conductive line has a connective section and a repair section at each end of the connective section. Each repair section occupies an area greater than the data distributing line. A broken data distributing line is repaired through the formation of an electrical connection between the repair sections at each end of the conductive line and the data distributing line.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: June 21, 2005
    Assignee: Au Optronics Corporation
    Inventor: Han-Chung Lai
  • Patent number: 6885066
    Abstract: A buried insulating film is formed in an LDD region between a source region and a drain region, and a non-doped silicon film is formed in the SOI layer above the buried insulating film. The SOI layer lying under the buried insulating film has a body concentration of 1018 cm?3.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 26, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Noriyuki Miura
  • Patent number: 6881615
    Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm?3 or lower, preferably 1×1019 atoms·cm?3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: April 19, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Naoto Kusumoto, Yasuhiko Takemura