Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.

Abstract: A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.

Abstract: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.

Abstract: A method for manufacturing TFTs is provided. It can be applied to both inverted staggered and co-planar TFT structures. The manufacturing method for the staggered TFT includes the formation of a gate electrode, a gate insulator, an active channel layer, a drain electrode, and a source electrode on a substrate. It emphasizes the use of metal oxides or II-VI compound semiconductors and low-temperature CBD process to form the active channel layer. In a CBD process, the active channel layers are selectively deposited on the substrates immersed in the solution through controlling solution temperature and PH value. The invention offers the advantages of low deposition temperature, selective deposition, no practical limit of panel size, and low fabrication cost. Its low deposition temperature allows the use of flexible substrates, such as plastic substrates.

Abstract: The present invention provides an image display unit and a method for manufacturing the same, in which the number of photolithographic processes can be reduced in the manufacture of an active substrate, and the manufacturing cost can be decreased. In a bottom gate type TFT substrate, a transparent conductive film 16 in the same layer as a pixel electrode 3 is used as a bottom layer, said pixel electrode 3 having said gate electrode 4 on main surface of an insulating substrate 1, and a laminated electrode film with a metal film 26 superimposed on a top layer thereof, and said pixel electrode 3 is used as the transparent conductive film 16.

Abstract: Embodiments of methods, apparatuses, devices, and/or systems for forming a thin film component are described.

Abstract: A method of manufacturing a thin film semiconductor device which includes a thin film transistor having a first semiconductor layer, a gate insulating layer, and a gate electrode which are laminated in this order on a substrate, and a capacitive element having a lower electrode that conductively connects a second semiconductor layer coplanar with the first semiconductor layer, a dielectric layer coplanar with the gate insulating layer, and an upper electrode coplanar with the gate electrode which are laminated in this order on the substrate is provided. The method includes, after simultaneously forming the gate insulating layer and the dielectric layer, and before forming the gate electrode and the upper electrode, introducing dopants into the second semiconductor layer from a first opening of a mask formed on a surface of the substrate to form the lower electrode, and etching a surface of the dielectric layer from the first opening of the mask.

Abstract: A semiconductor device having high operating performance and reliability is disclosed, and its fabrication process is also disclosed. In an n-channel type TFT 302, an Lov region 207 is disposed, whereby a TFT structure highly resistant to hot carriers is realized. Further, in an n-channel type TFT 304 forming a pixel portion, Loff regions 217 to 220 are disposed, whereby a TFT structure having a low OFF-current value is realized. In this case, in the Lov region, the n-type impurity element exists at a concentration higher than that of the Loff regions, and the whole of the n-type impurity region (b) which constitutes the Lov region is sufficiently activated by optical annealing, so that a good junction portion is formed between the n-type impurity region and the channel forming region.

Abstract: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b), a semiconductor film (106) and a protective film (107) are sequentially formed and layered without exposing them to the air. Further, the semiconductor film (106) is irradiated with laser light through the protective film (107). In this way, a TFT may be given good characteristics by completely purifying the interface of the semiconductor film.

Abstract: The invention is concerned with the fabrication of a MIS semiconductor device of high reliability by using a low-temperature process. Disclosed is a method of fabricating a MIS semiconductor device, wherein doped regions are selectively formed in a semiconductor substrate or a semiconductor thin film, provisions are then made so that laser or equivalent high-intensity light is radiated also onto the boundaries between the doped regions and their adjacent active region, and the laser or equivalent high-intensity light is radiated from above to accomplish activation.

Abstract: Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

Abstract: A method for manufacturing a thin film transistor results in a thin film transistor including a semiconductor film, a channel region provided in the semiconductor film, source and drain regions sandwiching the channel region, and a gate electrode facing the channel region with an intermediary of a gate insulating film. The method includes depositing a droplet that includes a semiconductor material on a substrate; and forming the semiconductor film by drying the droplet to precipitate the semiconductor material on at least a peripheral edge of the droplet.

Abstract: An organic electro-luminescent display and a method of fabricating the same include an organic light emitting diode, a driving transistor which drives the organic light emitting diode, and a switching transistor which controls an operation of the driving transistor, wherein active layers of the switching and driving transistors are crystallized using silicides having different densities such that the active layer of the driving transistor has a larger grain size than the active layer of the switching layer.

Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

Abstract: A low temperature polysilicon thin film transistor and method of manufacturing the same is provided. The low temperature polysilicon thin film transistor comprises a channel region. Among others, one feature of the method according to the present invention is the performance of a plasma treatment to adjust the threshold voltage of the low temperature polysilicon thin film transistor. Because the threshold voltage of the low temperature polysilicon thin film transistor can be adjusted through a plasma treatment, the manufacturing process is more flexible.

Abstract: A thin-film transistor and method for fabricating a thin-film transistor is disclosed. In the method, a controlled micro-line is formed by inkjet printing in combination with the coffee ring effect. The micro-line may be a semiconductor or an insulator. A high-current thin-film transistor utilizing the micro-line of the coffee ring as a channel is formed. A high current TFT can be achieved by utilizing the micro-line structure of the coffee ring ridge as a TFT channel.

Abstract: A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A first passivation layer can be formed on at least portions of the mesa sidewalls and on the substrate adjacent the mesa sidewalls wherein at least a portion of the mesa surface is free of the first passivation layer and wherein the first passivation layer comprises a first material. A second passivation layer can be formed on the first passivation layer wherein at least a portion of the mesa surface is free of the second passivation layer, and wherein the second passivation layer comprises a second material different than the first material. Related devices are also discussed.

Abstract: Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

Abstract: An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.

Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.

Abstract: To provide a method of efficiently configuring a circuit requiring high inter-device consistency by using thin-film transistors. A semiconductor layer is formed on a substrate and is patterned into desired shapes to form first semiconductor islands. The first semiconductor islands are uniformly crystallized by laser irradiation within the surface areas thereof. Thereafter, the semiconductor layers are patterned into desired shapes to become active layers of the thin-film transistors layer. Active layers of all of thin-film transistors constituting one unitary circuit are formed of one of the first semiconductor islands in this case. Thus, the TFTs mutually realize high consistency.

Abstract: A semiconductor film serving as an active region of a thin film transistor and an upper oxide film protecting the semiconductor film are dry etched to form the active region. In this case, a fluorine-based gas is used as the etching gas, and the etching gas is switched from the fluorine-based gas to a chlorine-based gas at a point of time when a lower oxide film as an underlying film of the semiconductor film is exposed. As the fluorine-based gas, a mixed gas of CF4 and O2 is used, and suitably, a gas ratio of CF4 and O2 in the mixture gas is set at 1:1, and the dry etching is performed therefor. By this etching, a side face of a two-layer structure of the semiconductor film and upper oxide film is optimally tapered, and a crack or a disconnection is prevented from being occurring in a film crossing over the two-layer structure.

Abstract: An individual identifier is easily provided in a semiconductor device capable of wireless communication. The semiconductor device includes a thin film transistor including a channel forming region, an island-like semiconductor film including a source region and a drain region, a gate insulating film, and a gate electrode; an interlayer insulating film; a plurality of contact holes formed in the interlayer insulating film which reach one of the source region and the drain region; and a single contact hole which reaches the other of the source region and the drain region, wherein a diameter of the single contact hole is larger than a diameter of each of the plurality of contact holes, and a sum of areas of bases of the plurality of contact holes is equal to an area of a base of the single contact hole.

Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.

Abstract: A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

Abstract: The present invention provides a highly stable light emitting device having high light-emitting efficiency (light-extraction efficiency) with high luminance and low power consumption, and a method of manufacturing thereof. A partition wall and a heat-resistant planarizing film are formed of a same material so as to be well-adhered to each other, thereby reducing material costs. Either an anode or a cathode is formed on the heat-resistant planarizing film. The partition wall and the heat-resistant planarizing film is adhered to each other without inserting a film having different refractive index therebetween, and therefore reflection of light is not caused in an interface.

Abstract: A method for forming a pattern of a stacked film, includes steps (a) to (e). The step (a) is forming sequentially a first base insulating film and a light shielding material on a transparent substrate. The step (b) is patterning the light shielding material to obtain a light shielding film with a first pattern. The step (c) is forming sequentially a second base insulating film, a semiconductor film and a first oxide film on a substrate. The step (d) is forming a resist pattern with a second pattern on the first oxide film. The step (e) is forming a pattern of a stacked film by dry etching the first oxide film and the semiconductor film, above the light shielding film. The stacked film includes the semiconductor film and the first oxide film. The dry etching includes an etching by using an etching gas and the resist pattern as a mask. The semiconductor film includes a taper angle which is controlled to be within predetermined range.

Abstract: A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

Abstract: Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes, In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode.

Abstract: Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor.

Abstract: Island-like semiconductor films and markers are formed prior to laser irradiation. Markers are used as positional references so as not to perform laser irradiation all over the semiconductor within a substrate surface, but to perform a minimum crystallization on at least indispensable portion. Since the time required for laser crystallization can be reduced, it is possible to increase the substrate processing speed. By applying the above-described constitution to a conventional SLS method, a means for solving such problem in the conventional SLS method that the substrate processing efficiency is insufficient, is provided.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a first insulating layer and a semiconductor layer in sequence on the gate line; depositing a conductive layer on the semiconductor layer; photo-etching the conductive layer and the semiconductor layer; depositing a second insulating layer; photo-etching the second insulating layer to expose first and second portions of the conductive layer; forming a pixel electrode on the first portion of the conductive layer; removing the second portion of the conductive layer to expose a portion of the semiconductor layer; and forming a light blocking member on the exposed portion of the semiconductor layer, the light blocking member having an opening exposing the pixel electrode.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: Methods of forming thin film devices with different electrical characteristics on a substrate comprising a driver circuit region and a pixel region. A first and a second polysilicon pattern layers are formed on the driving circuit region and the pixel region of the substrate, respectively. A first ion implantation is performed on the second polysilicon pattern layer using a masking layer covering the first polysilicon pattern layer as an implant mask, such that the first polysilicon pattern layer has an impurity concentration different from the second polysilicon pattern layer. After removal of the masking layer, a gate dielectric layer and a gate are successively formed on each of the first and second polysilicon pattern layers and a source/drain region is subsequently formed in each of the first and second polysilicon pattern layers to define a channel region therein.

Abstract: Disclosed is a method of manufacturing a photoreceiver, including sequentially laminating a buffer layer, a channel layer, a barrier layer, and a cap layer on a substrate; forming a mesa for HEMT and MSM PD by removing the buffer layer, the channel layer, the barrier layer, and the cap layer with the exception of a region corresponding to HEMT and MSM PD; forming a source electrode and a drain electrode of HEMT; removing the cap layer from a region corresponding to a gate electrode of HEMT and a Schottky electrode of MSM PD; forming the gate electrode of HEMT and the Schottky electrode of HEMT on the cap layer-removed region; and removing the cap layer, the barrier layer and the channel layer from a region corresponding to an optical waveguide, to expose the optical waveguide.

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

Abstract: Non-uniformity of the sheet resistance associated with ion implantation into a polysilicon semiconductor layer using a ribbon-shaped beam is minimized to prevent variations in the characteristics of fabricated thin film transistors. When the implanted ions are of a first element, a second element that is heavy and has no influence on electric charge is implanted at a critical implantation quantity or more into a dose region of the polysilicon semiconductor layer into which the ions of the first element are implanted.

Abstract: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

Abstract: The present invention improves the quality of the TFT structure by avoiding photo-induced current, and lowers manufacturing costs by decreasing the number of masks required in the process, wherein the former is achieved by the stacked structure including a gate layer, an insulation layer, an amorphous silicon layer and an ohmic contact layer, and the latter is achieved by using the stacked structure as a mask and by exposing the substrate from the back surface.

Abstract: A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.

Abstract: In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate.

Abstract: The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems. The structures typically comprise a thin crystalline layer of silicon/germanium formed over a wide range of suitable substrates. The crystalline properties of the silicon/germanium can be controlled during formation of the silicon/germanium so that the material has a relaxed crystalline lattice and large crystalline grain sizes. The crystalline grain sizes can be sufficiently large so that transistor devices formed in association with the thin crystalline material have active regions utilizing only a single grain of the silicon/germanium material.

Abstract: A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

Abstract: A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Abstract: A dispensing device for dispensing at least two flowable substances includes a container with two separate coaxial compartments for containing two flowable substances, respectively. Independently operable dosing units are associated with each compartment. Each dosing unit communicates with its associated compartment through a valve flap. Each dosing unit also includes a spring-actuated plunger guided in a cylinder, with a valving mechanism for enabling a predetermined quantity of the associated flowable substance to be selectively dispensed.