Including Differential Oxidation Patents (Class 438/165)
  • Patent number: 10103021
    Abstract: A thermally oxidized heterogeneous composite substrate provided with a single crystal silicon film on a handle substrate, said heterogeneous composite substrate being obtained by, prior to a thermal oxidization treatment at a temperature exceeding 850° C., conducting an intermediate heat treatment at 650-850° C. and then conducting the thermal oxidization treatment at a temperature exceeding 850° C. According to the present invention, a thermally oxidized heterogeneous composite substrate with a reduced number of defects after thermal oxidization can be obtained.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: October 16, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shoji Akiyama, Yuji Tobisaka, Kazutoshi Nagata
  • Patent number: 9978602
    Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 22, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (Crolles 2) SAS, STMICROELECTRONICS SA
    Inventors: Heimanu Niebojewski, Yves Morand, Maud Vinet
  • Patent number: 9859174
    Abstract: A semiconductor device comprises a source/drain region arranged on a substrate and a first gate stack having a first length arranged on a first channel region of the substrate. A second gate stack having a second length is arranged on a second channel region of the substrate. The first length is greater than the second length.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 9754792
    Abstract: One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Garo Jacques Derderian
  • Patent number: 9171764
    Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ryan Ryoung Han Kim, Jason Cantone
  • Patent number: 9023695
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Nian-Fuh Cheng, Chen-Yu Chen, Ming-Feng Shieh, Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Lin
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8871645
    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
  • Publication number: 20140273363
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
  • Publication number: 20140252474
    Abstract: A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventor: QUALCOMM Incorporated
  • Patent number: 8828811
    Abstract: A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment and the oxygen doping treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress test (BT test) can be reduced.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8823105
    Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventor: Mao Katsuhara
  • Patent number: 8802491
    Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: August 12, 2014
    Assignee: Sony Corporation
    Inventor: Mao Katsuhara
  • Patent number: 8647935
    Abstract: A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Andreas Scholze
  • Patent number: 8603878
    Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8574972
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Patent number: 8569868
    Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Xuefeng Hua, Ying Zhang
  • Patent number: 8460985
    Abstract: A method of manufacturing a semiconductor for a transistor that includes forming a precursor layer by coating a surface of an insulation substrate with a precursor solution for an oxide semiconductor, forming an oxide semiconductor by oxidizing a portion of the precursor layer, and removing a remaining precursor layer except for the oxide semiconductor.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 11, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo-Kyoung Ahn, Seon-Pil Jang, Gug-Rae Jo, Hong-Suk Yoo, Chang-Hoon Kim, Min-Uk Kim, Ju-Han Bae
  • Patent number: 8372733
    Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: February 12, 2013
    Assignees: Soitec, Commissariat à l'Énergie Atomique
    Inventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
  • Patent number: 8329524
    Abstract: A surface emitting laser includes a lower multilayer mirror, an active layer, and an upper multilayer mirror stacked onto a substrate. A first current confinement layer having a first electrically conductive region and a first insulating region is formed above or below the active layer using a first trench structure. A second current confinement layer having a second electrically conductive region and a second insulating region is formed above or below the first current confinement layer using a second trench structure. The first and second trench structures extend from a top surface of the upper multilayer mirror towards the substrate such that the second trench structure surrounds the first trench structure. When the surface emitting laser is viewed in an in-plane direction of the substrate, a boundary between the first electrically conductive region and the first insulating region is disposed inside the second electrically conductive region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: December 11, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mitsuhiro Ikuta
  • Patent number: 8324685
    Abstract: A fin-semiconductor region (13) is formed on a substrate (11). A first impurity which produces a donor level or an acceptor level in a semiconductor is introduced in an upper portion and side portions of the fin-semiconductor region (13), and oxygen or nitrogen is further introduced as a second impurity in the upper portion and side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: December 4, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Takayuki Kai, Yuichiro Sasaki
  • Patent number: 8324036
    Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Xuefeng Hua, Ying Zhang
  • Patent number: 8211786
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: July 3, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kangguo Cheng
  • Patent number: 8101512
    Abstract: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: January 24, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Gerhardt, Martin Trentzsch, Markus Forsberg, Manfred Horstmann
  • Patent number: 7932138
    Abstract: A method for manufacturing a thin film transistor with improved current characteristics and high electron mobility. According to the method, when an amorphous silicon thin film is crystallized into a polycrystalline silicon thin film by metal-induced crystallization, annealing conditions of the amorphous silicon thin film and the amount of a metal catalyst doped into the amorphous silicon thin film are optimized to reduce the regions of a metal silicide distributed at grain boundaries of the polycrystalline silicon thin film. In addition, oxygen (O2) gas or water (H2O) vapor is supplied to form a passivation film on the surface of the polycrystalline silicon thin film.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: April 26, 2011
    Assignee: Viatron Technologies Inc.
    Inventors: Hyoung June Kim, Dong Hoon Shin, Su Kyoung Lee, Jung Min Lee, Wang Jun Park, Sung Ryoung Ryu, Hoon Kim
  • Patent number: 7834398
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: November 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7834417
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Gordon P. Lee, Jiang-Kai Zuo
  • Patent number: 7816736
    Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: October 19, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7776669
    Abstract: A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, and including polycrystalline silicon having a constant directivity and a uniformly distributed crystal grain boundary; a gate insulating layer; a gate electrode; an interlayer insulating layer; and source and drain electrodes.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 17, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Ji-Su Ahn
  • Patent number: 7736963
    Abstract: In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong Lee, Young-Sub You, Hun-Hyeoung Leam, Yong-Woo Hyung, Jai-Dong Lee, Ki-Su Na, Jung-Hwan Kim
  • Patent number: 7622338
    Abstract: The present invention provides a method for forming a semiconductor region having a desired shape, and also provides a method for manufacturing a semiconductor device with few variations. Moreover, the present invention provides a method for manufacturing a semiconductor device which can reduce the cost with a small number of materials and with high yield. According to the present invention, after a semiconductor film is partially oxidized to form an oxide layer, the semiconductor film is etched using the oxide layer as a mask to form a semiconductor region having a desired shape, and thereafter a semiconductor device using the semiconductor region is manufactured. Thus, a semiconductor region having a desired shape can be formed in a predetermined position without using a known photolithography step using a resist.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: November 24, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Junko Sato
  • Publication number: 20090275177
    Abstract: A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
    Type: Application
    Filed: July 15, 2009
    Publication date: November 5, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ming Li, Kyoung-hwan Yeo, Sung-min Kim, Sung-dae Suk, Dong-won Kim
  • Patent number: 7605039
    Abstract: Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (?) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 20, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Tae Moon Roh, Jong Dae Kim
  • Publication number: 20090179266
    Abstract: Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Robert J. Gauthier, JR., Jed H. Rankin, Yun Shi, William R. Tonti
  • Patent number: 7510927
    Abstract: The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: Mark Bohr, Julie Tsai
  • Patent number: 7510919
    Abstract: The invention relates to a thin film having a thickness of less than 10 nm, made of oxidizable semi-conductor material and patterned in the form of patterns. To prevent the dewetting phenomenon of said patterns, lateral oxidized zones are arranged at the periphery of each pattern of the thin film so as to form an anchoring. This anchoring can be achieved by forming an oxide layer over the whole of the thin film and then depositing a nitride layer. Then the nitride and oxide layers and the thin film are patterned and the thin film is laterally oxidized so that each pattern of the thin film comprises, at the periphery thereof, an oxidized zone of predetermined width. The nitride and oxide layers are then removed so as to release the patterns oxidized at their periphery.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: March 31, 2009
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Charles Barbe, Maud Vinet, Béatrice Drevet, Carine Jahan
  • Patent number: 7504291
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7462519
    Abstract: A pair of substrates forming the active matrix liquid crystal display are fabricated from resinous substrates having transparency and flexibility. A thin-film transistor has a semiconductor film formed on a resinous layer formed on one resinous substrate. The resinous layer is formed to prevent generation of oligomers on the surface of the resinous substrate during formation of the film and to planarize the surface of the resinous substrate.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: December 9, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Satoshi Teramoto
  • Patent number: 7425480
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: September 16, 2008
    Assignee: Kabushiki Kaisha Tohisba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Publication number: 20080213952
    Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
    Type: Application
    Filed: May 5, 2008
    Publication date: September 4, 2008
    Inventors: Qi Xiang, James N. Pan, Jung-Suk Goo
  • Publication number: 20080128809
    Abstract: An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 5, 2008
    Inventor: Hideto Ohnuma
  • Patent number: 7381631
    Abstract: This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjacent to the deposited deformable material such that at least a portion of the oxidized portion of the oxidizable layer interacts with the at least one portion of the deformable material to apply a localized pressure upon the at least one portion of the deformable material.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 3, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Mardilovich, Pavel Kornilovich, Randy Hoffman
  • Patent number: 7344930
    Abstract: To obtain a semiconductor device containing TFTs of different, suitable properties as display pixel TFTs and high-voltage, driver-circuit TFTs, the semiconductor device of the present invention includes: first and second islands-shaped polycrystalline silicon (p-Si) layers provided above an insulating substrate and having relatively large grain sizes; a third islands-shaped p-Si layer having relatively small grain sizes; a first gate insulating film provided on the first p-Si layer and having a first thickness; second and third gate insulating films provided on the second and third p-Si layers having second and third thicknesses which are not less than the first thickness; gate electrodes provided on the gate insulating films; n-type high-concentration source/drain regions formed by adding an n-type impurity to a high concentration outside channel regions; and second and third n-type low-concentration-source/drain regions provided between the channel regions and the n-type high-concentration source/drain regi
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 18, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Patent number: 7303946
    Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: December 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Yasumasa Suizu, Yoshitaka Tsunashima
  • Patent number: 7288447
    Abstract: A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: October 30, 2007
    Inventors: Jian Chen, Thien T. Nguyen, Michael D. Turner, James E. Vasek
  • Patent number: 7214555
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate on which the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. The semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai
  • Patent number: 7196383
    Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: March 27, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Pooran Chandra Joshi, John W. Hartzell, Masahiro Adachi, Yoshi Ono
  • Patent number: 7183143
    Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Tzu-Yu Wang
  • Patent number: 7141459
    Abstract: A method of forming a multiple-thickness semiconductor-on-insulator, comprising the following steps. A wafer is provided comprising a semiconductor film (having at least two regions) overlying a buried insulator layer overlying a substrate. The semiconductor film within one of the at least two regions is masked to provide at least one semiconductor film masked portion having a first thickness, leaving exposed the semiconductor film within at least one of the at least two regions to provide at least one semiconductor film exposed portion having the first thickness. In one embodiment, at least a portion of the at least one exposed semiconductor film portion is oxidized to provide at least one partially oxidized, exposed semiconductor film portion. Then the oxidized portion of the exposed semiconductor film is removed to leave a portion of the semiconductor film having a second thickness less than the first thickness.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Liang Yang, Hao-Yu Chen, Yee-Chia Yeo, Carlos H. Diaz, Chenming Hu
  • Patent number: 7064018
    Abstract: A method of forming a semiconductor device includes fabricating digital circuits comprising a programmable logic circuit on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and fabricating a common interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: June 20, 2006
    Assignee: Viciciv Technology
    Inventor: Raminda Udaya Madurawe