Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.

Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.

Abstract: A Method for manufacturing a transistor comprising: a) amorphization and doping, by means of one or more localised implantation(s), of given regions of source and drain blocks based on crystalline semi-conductor material lying on an insulating layer of a semi-conductor on insulator substrate, the implantation(s) being carried out so as to conserve at the surface of said blocks zones of crystalline semi-conductor material on the regions of amorphous semi-conductor material, b) recrystallization of at least one portion of said given regions.

Abstract: A method of manufacturing a low temperature polysilicon film comprises: providing a substrate on a platform; forming a buffer layer on said substrate; forming an amorphous silicon layer on said buffer layer; and heating and annealing said amorphous silicon layer to allow said amorphous silicon layer to form a polycrystalline silicon layer; wherein a thermal insulating layer is formed on a bottom surface of said substrate or a top surface of the platform, before said buffer layer is formed on said substrate.

Abstract: Laser crystallization equipment includes a laser generator generating a laser beam, the laser beam being directed toward a processing target substrate, and a blade member over the processing target substrate, the blade member being configured to chop the laser beam with a predetermined width in two directions, wherein two ends of the laser beam chopped by the blade member are irradiated to the processing target substrate as diffraction light.

Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract: A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer.

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.

Abstract: A method of manufacturing a thin-film semiconductor device according to the present disclosure includes: preparing a substrate; forming a gate electrode above the substrate; forming a first insulating film on the gate electrode; forming a semiconductor thin film that is to be a channel layer, on the first insulating film; forming a second insulating film on the semiconductor thin film; irradiating the second insulating film with a beam so as to increase a transmittance of the second insulating film; and forming a source electrode and a drain electrode above the channel layer.

Abstract: A method of forming a metal pattern is disclosed. In the method, a metal layer is formed on a base substrate. A photoresist composition is coated on the metal layer to form a coating layer. The photoresist composition includes a binder resin, a photo-sensitizer, a mercaptopropionic acid compound and a solvent. The coating layer is exposed to a light. The coating layer is partially removed to form a photoresist pattern. The metal layer is patterned by using the photoresist pattern as a mask.

Abstract: A thin film transistor (TFT) and an organic light emitting diode (OLED) display device. The TFT and the OLED display device include a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate electrode insulated from the semiconductor layer, a gate insulating layer insulating the semiconductor layer from the gate electrode, and source and drain electrodes insulated from the gate electrode and partially connected to the semiconductor layer, wherein the semiconductor layer is formed from a polycrystalline silicon layer crystallized by a metal catalyst and the metal catalyst is removed by gettering using an etchant. In addition, the OLED display device includes an insulating layer disposed on the entire surface of the substrate, a first electrode disposed on the insulating layer and electrically connected to one of the source and drain electrodes, an organic layer, and a second electrode.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract: A thin film transistor (TFT) having an active layer pattern, the active layer pattern including a first active layer pattern extending in a first direction; a second active layer pattern extending in the first direction and parallel to the first active layer pattern; and a third active layer pattern connecting a first end of the first active layer pattern to a first end of the second active layer pattern.

Abstract: This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.

Abstract: A thin film transistor (TFT), an OLED device having the TFT and a method of fabricating the same and a method of fabricating an organic light emitting diode (OLED) display device that includes the TFT. The method of fabricating a TFT includes providing a substrate, forming a buffer layer on the substrate, forming an amorphous silicon layer pattern on the buffer layer, forming a metal layer on an entire surface of the substrate, forming a semiconductor layer by applying an electrical field to the metal layer to crystallize the amorphous silicon layer pattern, forming source and drain electrodes connected to the semiconductor layer by patterning the metal layer, forming a gate insulating layer on the entire surface of the substrate, forming a gate electrode on the gate insulating layer to correspond to the semiconductor layer and forming a protective layer on the entire surface of the substrate.

Abstract: An embodiment of the present invention provides a thin film transistor and a manufacturing method thereof and an array substrate comprising the thin film transistor.

Abstract: A thin-film transistor device manufacturing method and others according to the present disclosure includes: forming a plurality of gate electrodes above a substrate; forming a gate insulating layer on the plurality of gate electrodes; forming an amorphous silicon layer on the gate insulating layer; forming a buffer layer and a light absorbing layer above the amorphous silicon layer; forming a crystalline silicon layer by crystallizing the amorphous silicon layer with heat generated by heating the light absorbing layer using a red or near infrared laser beam; and forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, and film thicknesses of the gate insulating layer, the amorphous silicon layer, the buffer layer, and the light absorbing layer satisfy predetermined expressions.

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, masking portions of each fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

Abstract: A method for manufacturing array substrate with embedded photovoltaic cell includes: providing a substrate; forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; converting the amorphous silicon layer into a polysilicon layer; forming a pattern on the polysilicon layer; forming a first photoresist pattern on the polysilicon layer and injecting N+ ions; forming a gate insulation layer on the polysilicon layer; forming a second photoresist pattern on the gate insulation layer and injecting N? ions; forming a third photoresist pattern on the gate insulation layer and injecting P+ ions; forming a metal layer on the gate insulation layer so as to form a gate terminal; forming a hydrogenated insulation layer on the metal layer; forming a first ditch in the first insulation layer; and forming a second metal layer on the first insulation layer.

Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.

Abstract: A device for irradiating a laser beam onto an amorphous silicon thin film formed on a substrate. The device includes: a stage mounting the substrate; a laser oscillator for generating a laser beam; a projection lens for focusing and guiding the laser beam onto the thin film; a reflector for reflecting the laser beam guided onto the thin film; a controller for controlling a position of the reflector; and an absorber for absorbing the laser beam reflected by the reflector.

Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.

Abstract: The present invention provides a laser irradiation apparatus which can accurately control positions of beam spots of laser beams emitted from laser oscillators and the distance between the adjacent beam spots. A laser irradiation apparatus of the present invention includes a first movable stage with an irradiation body provided, two or more laser oscillators emitting laser beams, a plurality of second movable stages with the laser oscillators and optical systems provided, and a means for detecting at least one alignment maker. The first stage and the second stages may move not only in one direction but also in a plurality of directions. Further, the optical systems are to shape the laser beams emitted from the laser oscillators into linear beams on the irradiation surface.

Abstract: It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.

Abstract: A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.

Abstract: An amorphous semiconductor layer is formed over a first single crystal semiconductor layer provided over a glass substrate or a plastic substrate with an insulating layer therebetween. The amorphous semiconductor layer is formed by a CVD method at a deposition temperature of higher than or equal to 100° C. and lower than or equal to 275° C. with use of a silane-based gas not diluted. Heat treatment is performed so that the amorphous semiconductor layer solid-phase epitaxially grows. In such a manner, an SOI substrate including a thick single crystal semiconductor layer is manufactured.

Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: According to an aspect of the present invention, there is provided a thin-film transistor (TFT) sensor, including a bottom gate electrode on a substrate, an insulation layer on the bottom gate electrode, an active layer in a donut shape on the insulation layer, the active layer including a channel through which a current generated by a charged body flows, an etch stop layer on the active layer, the etch stop layer including a first contact hole and a second contact hole, and a source electrode and a drain electrode burying the first and second contact holes, the source and drain electrodes being disposed on the etch stop layer so as to face each other.

Abstract: A technique capable of improving performances of a semiconductor memory device provided with a recording film having a super lattice structure is provided. The semiconductor memory device records information by changing an electric resistance of a recording film by use of a change in an atomic arrangement of the recording film. Moreover, the recording film is provided with a stacked layer portion in which a first crystal layer and a second crystal layer made of chalcogen compounds having respectively different compositions are stacked, an orientation layer that enhances an orientation of the stacked layer portion, and an adhesive layer that improves the flatness of the orientation layer.

Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.

Abstract: A thin-film transistor device manufacturing method forms a plurality of gate electrodes above a substrate. A silicon nitride layer is formed on the plurality of gate electrodes. A silicon oxide layer is formed on the silicon nitride layer. An amorphous silicon layer is formed on the silicon oxide layer. The amorphous silicon layer is crystallized using predetermined laser light to produce a crystalline silicon layer. A source electrode and a drain electrode are formed on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Abstract: A display substrate includes a driving element, a switching element, a gate line, a data line, a driving voltage line and an electroluminescent element. The driving element includes a driving control electrode formed from a first conductive layer, and a driving input electrode and a driving output electrode formed from a second conductive layer. The switching element includes a switching control electrode formed from the second conductive layer, and a switching input electrode and a switching output electrode formed from a third conductive layer. The gate and data lines are formed from the second and third conductive layers, respectively. The driving voltage line is formed from the third conductive layer. Thus, misalignment between upper and lower patterns may be prevented to improve the reliability of a manufacturing process and increase an aperture ratio, thereby enhancing display quality.

Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

Abstract: An object of the present invention is to provide a method and a device for constantly setting the energy distribution of a laser beam on an irradiating face, and uniformly irradiating the laser beam to the entire irradiating face. Further, another object of the present invention is to provide a manufacturing method of a semiconductor device including this laser irradiating method in a process. Therefore, the present invention is characterized in that the shapes of plural laser beams on the irradiating face are formed by an optical system in an elliptical shape or a rectangular shape, and the plural laser beams are irradiated while the irradiating face is moved in a first direction, and the plural laser beams are irradiated while the irradiating face is moved in a second direction and is moved in a direction reverse to the first direction.

Abstract: A first thin film diode (100A) has a first semiconductor layer (10A) and a first light blocking layer (12A) disposed on the substrate side of the first semiconductor layer. A second thin film diode (100B) has a second semiconductor layer (10B) and a second light blocking layer (12B) disposed on the substrate side of the second semiconductor layer. An insulating film (14) is formed between the first semiconductor layer (10A) and the first light blocking layer (12A) and between the second semiconductor layer (10B) and the second light blocking layer (12B). A thickness D1 of a portion of the insulating film (14) positioned between the first semiconductor layer (10A) and the first light blocking layer (12A) is different from a thickness D2 of a portion of the insulating film (14) positioned between the second semiconductor layer (10B) and the second light blocking layer (12B).

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.

Abstract: A method for manufacturing oxide thin film transistors includes steps of: forming a gate, a drain electrode, a source electrode, and an oxide semiconductor layer respectively. The oxide semiconductor layer is formed on the gate electrode; the drain electrode and the source electrode are formed at two opposite sides of the oxide semiconductor layer. The method further includes a step of depositing a dielectric layer of silicon oxide, and a reacting gas for depositing the silicon oxide includes silane and nitrous oxide. A flow rate of nitrous oxide is in a range from 10 to 200 standard cubic centimeters per minute (SCCM). Oxide thin film transistors manufactured by above method has advantages of low leakage, high mobility, and other integrated circuit member can be directly formed on the thin film transistor array substrate of a display device.

Abstract: A display substrate includes first, second, and third insulating layers in a display area thereof. The first and third insulating layers are in not only the display area but also a pad area adjacent to the display area and including a pad therein. Thus, defects of the display panel may be reduced.

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.

Abstract: A crystalline silicon thin film is formed by irradiating a silicon thin film with a laser beam. The laser beam is a continuous wave laser beam. An intensity distribution of the laser beam in a first region about a center of the intensity distribution is symmetric on an anterior side and a posterior side of the center. The intensity distribution in a second region about the center is asymmetric on the anterior side and the posterior side. The first region is from the maximum intensity of the laser beam at the center to an intensity half of the maximum intensity. The second region is at most equal to the half of the maximum intensity of the laser beam. In the second region, an integral intensity value on the posterior side is larger than on the anterior side.

Abstract: A method of manufacturing a low temperature polysilicon film comprises: providing a substrate on a platform; forming a buffer layer on said substrate; forming an amorphous silicon layer on said buffer layer; and heating and annealing said amorphous silicon layer to allow said amorphous silicon layer to form a polycrystalline silicon layer; wherein a thermal insulating layer is formed on a bottom surface of said substrate or a top surface of the platform, before said buffer layer is formed on said substrate.

Abstract: Systems for processing thin films having variable thickness are provided. A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.

Abstract: A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.