Abstract: A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract: The present invention provides a semiconductor memory device capable of preventing bridge formations in a peripheral circuit region and improving a process margin and a method for fabricating the same. The semiconductor memory device includes: a cell region; a peripheral circuit region adjacent to the cell region; and a plurality of line patterns formed in the cell region and the peripheral circuit region, wherein a spacing distance between the line patterns is at least onefold greater than a width of the line pattern.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method of manufacturing a semiconductor device having self-aligned contact structure with side wall spacers and offset nitride films. The method includes forming the side wall spacers as having lower side wall spacers that are composed of silicon oxide films and that are in contact with lower sides of gate electrode side walls, and as having upper side wall spacers that are composed of silicon nitride films and that are in contact with upper sides of the gate electrodes side walls. A distance is thus formed between the device substrate and an interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurence of poor contact.

Abstract: The present invention relates to a method for fabricating a gate electrode of a semiconductor device with a double hard mask capable of preventing an abnormal oxidation of a metal layer included in the gate electrode and suppressing stress generation. The method includes the steps of: forming a gate insulation layer on a substrate; forming a gate layer structure containing at least a metal layer on the gate insulation layer; forming a hard mask oxide layer on the gate layer structure at a temperature lower than an oxidation temperature of the metal layer; forming a hard mask nitride layer on the hard mask oxide layer; patterning the hard mask oxide layer and the hard mask nitride layer as a double hard mask for forming the gate electrode; and forming the gate electrode by etching the gate layer structure with use of the double hard mask as an etch mask.

Abstract: According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

Abstract: A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region of the nanowire leaving exposed a second region and a third region of the nanowire. A first spacer is deposited on each side of the sacrificial gate stack. A second dielectric layer is deposited over the first dielectric layer to cover the second region and third region. The sacrificial gate stack is removed. The first region of the nanowire is thinned by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension.

Abstract: A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

Abstract: According to embodiments of the present invention, methods of manufacturing a semiconductor device, and semiconductor devices manufactured thereby, are provided. A field region is formed that defines active regions in a semiconductor substrate. Spaced apart gates are formed on the active regions in the semiconductor substrate. The gates have sidewalls that extend away from the semiconductor substrate. First spacers are formed on the sidewalls of the gates. Second spacers are formed on the first spacers and opposite to the gates. Ion impurities are implanted into the active regions in the semiconductor substrate, adjacent to the gates, using the first and second spacers as an ion implantation mask. A portion of the second spacers is removed to widen the gaps between the gates. A dielectric layer is formed on the semiconductor substrate in the gaps between the gates.

Abstract: A sub-0.05 ?m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 ?m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.

Abstract: A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask 21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n− layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

Abstract: Resist patterns (R11 and R12) are formed such that an opening between both the films is aligned to the position, where the source electrode (7) is formed, while the region on the N+-layer (5), where the drain electrode (8) is formed afterwards, is covered by the resist film (R11). After ohmic electrode material is applied from a direction perpendicular to a semiconductor substrate (1), the resist films (R11 and R12) are removed with the ohmic electrode films (OM11 and OM12). The remaining ohmic electrode film (OM14) functions as the source electrode (7). After the above-described first lift off process, the second lift off process is performed to form a drain electrode (8) on the N+-layer (5).

Abstract: An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

Abstract: A MOS transistor with a drain extension includes an isolation block on the upper surface of a semiconductor substrate. The isolation block has a first sidewall next to the gate of the transistor, and a second sidewall that is substantially parallel to the first sidewall. The isolation block further includes a drain extension zone in the substrate under the isolation block, and a drain region in contact with the drain extension zone. The drain region is in the substrate but is not covered by the isolation block.

Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.

Abstract: A method for forming a spacer layer adjoining a substantially vertical first sidewall of a topographic feature within a microelectronic product employs an anisotropic etching of a reentrant spacer material layer formed upon the topographic feature. The spacer layer is formed at least in part with a substantially vertical second sidewall laterally separated from the substantially vertical first sidewall. The method is useful for forming spacer layers within field effect transistor devices.

Abstract: A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A method of producing a semiconductor device able to prevent outward diffusion of an impurity from a gate electrode and improve the device quality, the method comprising the steps of forming a gate electrode made of a semiconductor layer on a substrate (preferably SOI substrate) via a gate insulating film, forming a first insulating film coating the gate electrode by ALD, forming a second insulating film on a first insulating film, introducing an impurity to a substrate (preferably silicon active layer of the SOI wafer) to form a source/drain region by self-alignment with respect to the gate electrode, and forming an interlayer insulating film on the second insulating film.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: The present invention provides a method for reducing loading capacitance.

Abstract: A data pad region of a liquid crystal display panel includes a plurality of data lines vertically arranged at specified intervals, a plurality of data pads respectively connected to the data lines, at least one first side contact with a first area formed in each data pad and at least one second side contact with a second area formed in each data pad, wherein the first area is larger than the second area.

Abstract: A PIN photodetector includes reduced parasitic capacitance and is suitable for high-speed applications. Metal interconnect leads are coupled to the photodetector and extend over electrically insulating regions which reduce or eliminate parasitic capacitance. The electrically insulating regions may be formed by a deep proton implantation process which introduces impurities into the N-type layer, P-type layer and intrinsic layer in portions of the inactive area according to one embodiment. In another embodiment, the electrically insulating regions may be formed by removing parts of the film stack that includes N-type layer, P-type layer and intrinsic layer, from portions of the inactive area, introducing impurities and optionally adding a dielectric material. The PIN photodetector may take on the shape of a mesa to provide contact to each of the upper and lower electrodes.

Abstract: Provided is a field emission device having a mesh gate. The object of this research is to provide a field emission display (FED) using a triode field emission device for preventing increase of operation voltage, and securing high concentration of electron beams. The operation properties of the FED is different based on a structure of an extraction electrode. In this research, the extraction electrode is formed on the electron emitting source and it has a plurality of openings corresponding to the locations of carbon nanotube mixture. The concentration of the electron beams is raised and leakage current is suppressed by using an insulating mesh gate plate. The upper part of the openings has a smaller diagram than the lower part. The high concentration of electron beams and little leakage current can be generated by adding auxiliary electrodes or optimizing the shape of electrodes.

Abstract: A fine electrode-forming masking member for forming fine gate electrodes, which can decrease gate length of a gate electrode of a field effect transistor. The method includes forming a first masking member having penetrating portions formed into opening patterns in conformity with the fine gate electrodes, on a semiconductor substrate using a photosensitive resin; and heating the first masking member so that parts of sidewalk in contact with the substrate of the penetrating portions flow along the semiconductor substrate to form extension portions. Accordingly, the widths of the penetrating portions at the bottom surface side are decreased so as to form the opening patterns. Gate electrodes are formed on regions of the semiconductor substrate exposed through the opening patterns while the substrate is masked with the fine electrode-forming masking member.

Abstract: A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

Abstract: A semiconductor device comprises an SAC structure having side wall spacers and offset nitride films. In particular, in this semiconductor device, the side wall spacers are constituted from lower side wall spacers that are composed of silicon oxide films and are in contact with the lower side of the gate electrode side walls, and upper side wall spacers that are composed of silicon nitride films and are in contact with the upper side of the gate electrodes side walls. As a result thereof, a distance is formed between the substrate and the interface between the silicon nitride film and the silicon oxide film. This suppresses the hot carrier phenomenon and the occurrence of poor contact.

Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.

Abstract: A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that contacts the floating gate 22, forming a control gate 28 over the second insulation layer 26, forming a source region 14 and a drain region 16 in the semiconductor layer 10, depositing a insulation layer 40 over the semiconductor layer 10, and etching the insulation layer 40 to form a sidewall insulation layer, wherein the etching of the insulation layer 40 is conducted such that the insulation layer 40 remains above the floating gate 40, and the floating gate 22 is not exposed.

Abstract: A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so that the conductive metal film covers the via-hole on one side of the first part; using an electrolytic plating process, where the conductive metal Film is used as an electrode, to form a metal via member within the via hole and to form an inter-layer wire; and removing an entirety of the conductive metal film without removing the inter-layer formed by the electrolytic plating process; repeating steps (a)-(e) for a second part; and thereafter attaching the first part to the second part.

Abstract: Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p channel in a p-well of the substrate and forming at least one n channel in the p-well of the substrate. A p-i-n photodetector is formed in the substrate by forming at least one p channel in an absorption region of the substrate when forming the at least one p channel in the p well of the FET and forming at least one n channel in the absorption region of the substrate when forming the at least one n channel in the p-well of the FET.

Abstract: A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the fine repetitive geometries. At least two working materials are used one of which can be etched without etching a substrate. In one embodiment the two working materials and the substrate are each etched independently. In other embodiments, the substrate and one working material have similar etch rates while the other material is etched independently. Pedestals are formed having an initial pitch. First sidewalls are formed around the pedestals. The pedestals are removed and a second and third sidewall are formed on the inside and outside surfaces of the first sidewall having spaces there-between. The first sidewall is removed generating another space between the second and third sidewall.

Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.

Abstract: A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C.

Abstract: A method of fabricating an RF lateral MOS device, comprising the following steps. A substrate having a gate oxide layer formed thereover is provided. A first layer of polysilicon is formed over the gate oxide layer. A second layer of material is formed over the polysilicon layer. The polysilicon and the second layer of material are patterned to form a gate having exposed sidewalls with the gate having a lower patterned polysilicon layer and an upper patterned second material layer. Sidewall spacers are formed on the exposed sidewalls of the gate. The upper patterned second material layer of the gate is removed to form a cavity above the patterned polysilicon layer and between the sidewall spacers. A planarized copper plug is formed within the cavity.

Abstract: There is provided a process for fabrication of a SIMOX substrate wherein oxygen ions are implanted into a single crystal silicon substrate and then subjected to a high-temperature heat treatment to form a buried oxide layer and a surface single crystal silicon layer, wherein the single crystal silicon substrate used has a mean resistivity of 100 &OHgr;cm or greater, and there is conducted a step of maintaining a temperature of from 800° C. to 1250° C. for a predetermined time in the final stage of the high-temperature heat treatment, as well as a SIMOX substrate wherein the mean resistivity of the substrate obtained by the process is 100 &OHgr;cm or greater.

Abstract: A method for fabricating electrically conductive silicon carbide articles by doping and sintering submicron silicon carbide particles using sub-micron alumina as the dopant source. Submicron alumina particles are made by milling aluminum powder. Despite the ductility of metallic aluminum, it is successfully ball milled in an aqueous medium through the creation and abrasion of successive layers of an alumina skin to yield alumina particles as small as 0.01 &mgr;m across. When suitably composed mixtures of the silicon carbide and alumina are molded into a green body and heated sufficiently in a non-oxidizing furnace atmosphere, the alumina breaks down to metallic aluminum which diffuses into the silicon carbide. The small particle sizes and the presence of a sintering aid enable rapid processing kinetics which favor saturation of the silicon carbide by the aluminum and inhibit grain growth.

Abstract: A method is provided for crystallizing a silicon film in liquid crystal display (LCD) fabrication. The method comprises: forming an amorphous silicon film having a thickness in the range of 100 to 1000 Angstroms (Å); irradiating the silicon film with a laser pulse having a pulse width of 50 nanoseconds (ns) or greater, as measured at the full-width-half-maximum (FWHM), using a beamlet width in the range of 3 to 20 microns; and, in response to irradiating the silicon film, laterally growing crystal grains. In one example, irradiating the silicon film may include irradiating with a pulse having a pulse width in the range between 30 and 300 ns FWHM, and an energy density in the range from 200 to 1300 millijoules per square centimeter (mJ/cm2).

Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 &mgr;m and a depth of 10 &mgr;m were formed at 10 &mgr;m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 &mgr;m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.

Abstract: A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.

Abstract: A method for growing strain-engineered, self-assembled, semiconductor quantum dots (QDs) into ordered lattices. The nucleation and positioning of QDs into lattices is achieved using a periodic sub-surface lattice built-up on a substrate, stressor layer, and spacer layer. The unit cell dimensions, orientation and the number of QDs in the basis are tunable. Moreover, a 2D lattice can be replicated at periodic intervals along the growth direction to form a three-dimensional (3D) lattice of QDs.

Abstract: A laser diode having an optical cavity which is formed on top of a semiconductor substrate and has semiconductor crystals and an oxide layer that is substantially free from arsenic oxide. The oxide layer may be formed by using the matrix of the optical cavity as a matrix or a layer formed by the hydrogenation or oxygenation of the matrix of the cavity on at least one side of the optical cavity. The laser diode has a long operational life and high reliability without facet degradation.

Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

Abstract: In a back-surface electrode type photoelectric conversion element having electrodes and semiconductor layers for collecting carriers disposed only on a back surface side of a semiconductor substrate, a semiconductor thin film that is larger in band gap than the semiconductor substrate and that contains an element causing a conductivity identical to or different from a conductivity of the semiconductor substrate is provided on a light-receiving surface side of the semiconductor substrate, and a diffusion layer is formed on a surface of the semiconductor substrate.

Abstract: A semiconductor device includes a multi-flexible substrate and semiconductor chips mounted thereon. The multi-flexible substrate is configured such that organic insulation substrate layers and filmy adhesive layers are alternatively stacked together and wiring layers formed therein are interconnected by means of vias. Each of the vias consisting of a via-hole which is formed penetrating both the organic insulation substrate layers and the filmy adhesive layers and a metal via member 26 which is provided in the via-hole and made of an identical material. A method of manufacturing the multi-flexible substrate for the semiconductor device is also disclosed.

Abstract: GaN-based FET has a sapphire substrate of about 50 nm thick on which an n-type GaN electron transit layer and an Al0.2Gao0.8N electron supply layer are formed, together with n+-type GaN contact regions sandwiching the electron transit and supply layers therebetween. On the entire faces of these layer and regions is formed a polyimide interlayer insulating film of about 3000 nm thick that is formed with contact holes in which source, drain and gate electrodes are formed, each of which is comprised of a TaSi/Au layer and about 5000 nm in thickness. The source and drain electrodes are ohmic-connected to the n+-type GaN contact regions and the gate electrode is in contact with an SiO2 gate insulating film.