Lateral Bipolar Transistor Patents (Class 438/204)
  • Patent number: 10224423
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: March 5, 2019
    Assignee: STMircoelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Patent number: 9799652
    Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Natalie B. Feilchenfeld, Michael J. Zierak, Theodore J. Letavic, Yun Shi, Santosh Sharma
  • Patent number: 9293569
    Abstract: A bipolar junction transistor is provided with an emitter region, an oxide region, a base region and a collector region. The base region is located between the emitter region and the oxide region and has a junction with the emitter region and an interface with the oxide region. An at least partially conductive element such as metal or silicon is positioned to overlap with at least part of the junction between the base region and the emitter region, thereby forming a gate. The gate also overlaps with at least part of the interface between the base region and the oxide region. When a suitable bias voltage is applied to the gate, the gain of the transistor can be increased.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 22, 2016
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Brendan Toner, Xuezhou Cao, Fred Fang, Chuan Chien Tan
  • Patent number: 9029955
    Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 12, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 8975130
    Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8946040
    Abstract: A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning
  • Patent number: 8859361
    Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: October 14, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Publication number: 20140302647
    Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 9, 2014
    Inventor: Madhur Bobde
  • Patent number: 8772837
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11. An emitter electrode 31A and a collector electrode 31B are formed in the open region 21 and are composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 8, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8603873
    Abstract: A method for forming a bipolar junction transistor comprises forming a first well of a second conductive type for forming a collector region in a substrate including device isolation layers, wherein the substrate comprises a first conductive type, forming a second well of the first conductive type for a metal-oxide-semiconductor transistor of the second conductive type within the first well of the second conductive type, wherein the second well of the first conductive type is formed deeper than the device isolation layers, forming a shallow third well of the first conductive type for a base region within the first well of the second conductive type, wherein the shallow third well of the first conductive type is formed shallower than the device isolation layers, and simultaneously forming an emitter region within the shallow third well of the first conductive type and a plurality of collector contacts within the first well of the second conductive type by performing an ion implantation process for forming sour
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Don Kim
  • Patent number: 8574973
    Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 5, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8569866
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: October 29, 2013
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8530298
    Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: September 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Richard G. Roybal, Shariq Arshad, Shaoping Tang, James Fred Salzman
  • Patent number: 8455315
    Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 4, 2013
    Inventor: Madhur Bobde
  • Patent number: 8431450
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 8415764
    Abstract: An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: April 9, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Wen Chung, Po-Yao Ke, Wei-Yang Lin, Shine Chung
  • Patent number: 8405148
    Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: March 26, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8330223
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Klaus Schimpf, Manfred Schiekofer, Carl David Willis, Michael Waitschull, Wolfgang Ploss
  • Patent number: 8299532
    Abstract: An ESD protection device structure includes a well having a first conductive type, a first doped region having a second conductive type disposed in the well, a second doped region having the first conductive type, and a third doped region having the second conductive type disposed in the well. The second doped region is disposed within the first doped region so as to form a vertical BJT, and the first doped region, the well and the third doped region forms a lateral BJT, so that pulse voltage that the ESD protection structure can tolerate can be raised.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Hsiang Lai, Kuei-Chih Fan, Tien-Hao Tang
  • Patent number: 8173500
    Abstract: A poly-emitter type bipolar transistor includes a buried layer formed over an upper portion of a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a collector area formed on the epitaxial layer and connected to the buried layer, a base area formed at a part of an upper portion of the epitaxial layer, and a poly-emitter area formed on a surface of the semiconductor substrate in the base area and including a polysilicon material. A BCD device includes a poly-emitter type bipolar transistor having a poly-emitter area including a polysilicon material and at least one of a CMOS and a DMOS formed on a single wafer together with the poly-emitter type bipolar transistor.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: May 8, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Bon-Keun Jun
  • Patent number: 8143671
    Abstract: A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Patent number: 8129234
    Abstract: A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas A. Wallner, Ebenezer E. Eshun, Daniel J. Jaeger, Phung T. Nguyen
  • Patent number: 8115280
    Abstract: An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Shuo-Mao Chen, Chin-Wei Kuo, Sally Liu
  • Patent number: 8114696
    Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 14, 2012
    Assignee: Intellectual Ventures II LLC
    Inventor: Hee-Jeong Hong
  • Publication number: 20110300678
    Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 8, 2011
    Inventor: Madhur Bobde
  • Patent number: 8071436
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. In some implementations, a method of fabricating a semiconductor device is provided that includes forming an LDMOS transistor having a first drain with a first drain-side n+ region, a first source with a first source-side n+ region and a first source-side p+ region, and a first gate between the first drain and the first source on the substrate. The method also includes forming an n-type CMOS transistor having a second drain having a second drain-side n+ region, a second source having a second source-side n+ region, and a second gate between the second drain and the second source. In so doing, the LDMOS transistor can be fabricated through a process that can be seamlessly integrated into a sub-micron CMOS process.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 6, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Publication number: 20110266630
    Abstract: A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
    Type: Application
    Filed: December 19, 2008
    Publication date: November 3, 2011
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Tomislav Suligoj, Marko Koricic, Hidenori Mochizuki, Soichi Morita
  • Patent number: 8021956
    Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: September 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
  • Patent number: 7981739
    Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: July 19, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7939400
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: May 10, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Ting Tsui, Satyavolu S. Papa Rao, Haowen Bu, Robert Kraft
  • Patent number: 7932581
    Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region surrounding the base region with an offset between an edge of the gate and the collector region; a lightly doped drain region between the edge of the gate and the collector region; a salicide block layer disposed on or over the lightly doped drain region; and a collector salicide formed on at least a portion of the collector region.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: April 26, 2011
    Assignee: Mediatek Inc.
    Inventors: Ming-Tzong Yang, Ching-Chung Ko, Tung-Hsing Lee, Zheng Zeng
  • Patent number: 7875513
    Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: January 25, 2011
    Inventors: Fabio Pellizzer, Roberto Bez, Paola Zuliani, Augusto Benvenuti
  • Patent number: 7868378
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 11, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Patent number: 7863173
    Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: January 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Jae Kang, Gyuhwan Oh, Insun Park, Hyunseok Lim, Nak-Hyun Lim
  • Patent number: 7829405
    Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 9, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Kamel Benaissa
  • Publication number: 20100173459
    Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 8, 2010
    Inventors: Daniel Charles Kerr, Michael Scott Carroll, Amal Ma Hamad, Thiet The Lai, Roger W. Key
  • Publication number: 20100164012
    Abstract: A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter.
    Type: Application
    Filed: December 29, 2009
    Publication date: July 1, 2010
    Inventor: Yeo-Cho Yoon
  • Patent number: 7723172
    Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 25, 2010
    Assignee: Icemos Technology Ltd.
    Inventor: Takeshi Ishiguro
  • Patent number: 7701038
    Abstract: A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: April 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Chih-Ping Chao, Chih-Sheng Chang
  • Patent number: 7696536
    Abstract: A method for enhancing operation of a bipolar light-emitting transistor includes the following steps: providing a bipolar light-emitting transistor having emitter, base, and collector regions; providing electrodes for coupling electrical signals with the emitter, base, and collector regions; and adapting the base region to promote carrier transport from the emitter region toward the collector region by providing, in the base region, several spaced apart quantum size regions of different thicknesses, with the thicknesses of the quantum size regions being graded from thickest near the collector to thinnest near the emitter.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: April 13, 2010
    Assignee: The Board of Trustees of The University of Illinois
    Inventors: Milton Feng, Nick Holonyak, Jr.
  • Patent number: 7666731
    Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: February 23, 2010
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7659583
    Abstract: An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Zhibin Ren, Ghavam Shahidi, Dinkar V. Singh, Jeffrey W. Sleight, Xinhui Wang
  • Patent number: 7642154
    Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7585717
    Abstract: A method for manufacturing a semiconductor device includes: forming a lower gate electrode over a substrate; forming a sacrifice film over the substrate such that the lower gate electrode is overlapped with the sacrifice film; forming a semiconductor film over the sacrifice film such that the semiconductor film crosses over the lower gate electrode; removing the sacrifice film; forming a lower gate insulating film in an empty space between the lower gate electrode and the semiconductor film, the empty space being obtained by removing the sacrifice film; forming an upper gate insulating film over the semiconductor film; and forming an upper gate electrode over the upper gate insulating film, the upper gate electrode being electrically connected to the lower gate electrode.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: September 8, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 7465621
    Abstract: A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the transistor to have a second surface area in the first surface area of the first impurity region. A gate oxide is formed after implantation of the second impurity region between a source region and the drain region of the transistor, and the gate oxide is covered with a conductive material. A third impurity region of the opposite second type and a fourth impurity region of the first type are implanted into the source region of the transistor in the first surface area. A fifth impurity region of the opposite second type is implanted into the drain region of the transistor in the second surface area of the second impurity region.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: December 16, 2008
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga, Andrew J. Burstein
  • Patent number: 7445983
    Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: November 4, 2008
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoto Fujishima, C. Andre T. Salama
  • Patent number: 7445982
    Abstract: A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: November 4, 2008
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoto Fujishima, C. Andre T. Salama
  • Publication number: 20080169513
    Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.
    Type: Application
    Filed: September 28, 2007
    Publication date: July 17, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Marie Denison
  • Patent number: 7381606
    Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 3, 2008
    Assignee: Cambridge Semiconductor Limited
    Inventor: Florin Udrea