Abstract: An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base).

Abstract: In a manufacturing method for lateral bipolar transistors on an SOI substrate, a ridge-shaped gate electrode (8/9) is applied onto a mesa (3) provided with a basic doping and is covered surface-wide with a TEOS layer (10) that has vertical portions functioning as spacers (11,12) at the sidewalls of this gate electrode. Dopants for a collector region (4) and an emitter region (6) are introduced using lacquer masks (13,14). After the removal of the TEOS layer (10), the base implantation ensues in the region of the spacer (11) along an edge of the gate electrode.

Abstract: A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body electrically coupled to the base. A reverse-bias at the emitter-base junction, which is less than a breakdown voltage for the emitter-base junction, activates the MOS transistor which substantially reduces the resistance between the emitter and the base. Preferably, a first semiconductor region provides both the drain and the emitter, and a second semiconductor region provides both the body and the base, for reduced surface area on an integrated circuit chip.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.

Abstract: A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.

Abstract: A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with conventional lateral bipolar transistors, thus improving f.sub.t and f.sub.max. The polysilicon emitter and collector contacts improve the emitter efficiency and current gain, and allows for more flexible contact placement. The process is compatible with conventional double-poly bipolar processes.