Including Additional Vertical Channel Insulated Gate Field Effect Transistor Patents (Class 438/209)
  • Patent number: 9716168
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer 32 of a first conductivity type, a silicon carbide layer 36 of a second conductivity type, a gate trench 20, a gate electrode 79 provided in the gate trench 20, and a protection trench 10 formed to a depth greater than the gate trench 20. A region in the horizontal direction that includes both the gate trench 20 and a protection trench 10 that surrounds the gate trench 20 with at least a part of the gate trench 20 left unenclosed is a cell region, and a region in the horizontal direction that includes a protection trench 10 and in which a gate pad 89 or a lead electrode connected to the gate pad is disposed is a gate region.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 25, 2017
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Tetsuto Inoue, Akihiko Sugai, Shunichi Nakamura
  • Patent number: 9147690
    Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 29, 2015
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Wen-Hao Lee
  • Patent number: 9054216
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Patent number: 9053981
    Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.
    Type: Grant
    Filed: March 2, 2014
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8921218
    Abstract: A method and device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
  • Patent number: 8790977
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Patent number: 8709888
    Abstract: A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a PDSOI device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the PDSOI device on the same SOI substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8698235
    Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 15, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8637370
    Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 28, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Yi Liang, Dong Yemin
  • Patent number: 8609488
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Patent number: 8563376
    Abstract: A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8470658
    Abstract: A semiconductor integrated circuit device and method of fabricating a semiconductor integrated circuit device, the method including preparing a first conductivity type substrate including a first conductivity type impurity such that the first conductivity type substrate has a first impurity concentration; forming a buried impurity layer using blank implant such that the buried impurity layer includes a first conductivity type impurity and has a second impurity concentration higher than the first impurity concentration; forming an epitaxial layer on the substrate having the buried impurity layer thereon; and forming semiconductor devices and a device isolation region in or on the epitaxial layer.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: June 25, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Don Kim, Hoon Chang, Seo-In Pak
  • Patent number: 8466007
    Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 18, 2013
    Assignee: General Electric Company
    Inventors: Eladio Clemente Delgado, Richard Alfred Beaupre, Stephen Daley Arthur, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion
  • Patent number: 8450175
    Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi, Suraj J. Mathew, Kamal M. Karda, Hung-Ming Tsai
  • Patent number: 8445343
    Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Kihyun Hwang, Sangryol Yang, Yong-Hoon Sang, Ju-Eun Kim
  • Patent number: 8440916
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 8409948
    Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Sanh D. Tang
  • Patent number: 8361856
    Abstract: A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: January 29, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Lars Heineck, Jaydip Guha
  • Patent number: 8357572
    Abstract: The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: January 22, 2013
    Assignee: 658868 N.B. Inc.
    Inventors: Sang Don Lee, Sung Woong Chung
  • Patent number: 8343820
    Abstract: A method for fabricating a vertical channel type non-volatile memory device including a plurality of memory cells stacked along channels protruding from a substrate includes: alternately forming a plurality of first material layers and a plurality of second material layers over the substrate; forming a buffer layer over the substrate with the plurality of the first material layers and the plurality of the second material layers formed thereon; forming trenches by etching the buffer layer, the plurality of the second material layers, and the plurality of the first material layers; forming a material layer for channels over the substrate to fill the trenches; and forming the channels by performing a planarization process until a surface of the buffer layer is exposed.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young-Kyun Jung
  • Patent number: 8324668
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ping Huang, Chih-Hsiang Huang, Ka Hing Fung, Chung-Cheng Wu, Haiting Wang
  • Patent number: 8314340
    Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: November 20, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Sho Akai, Tatsuya Imai, Iku Tokihisa
  • Patent number: 8299525
    Abstract: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: October 30, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Alberto O. Adan, Mitsuhiro Kikuta
  • Patent number: 8298889
    Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 30, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
  • Patent number: 8288220
    Abstract: A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: October 16, 2012
    Assignee: Cree, Inc.
    Inventors: Brett Adam Hull, Qingchun Zhang
  • Patent number: 8222076
    Abstract: A process for fabricating a semiconductor layer of an electronic device including: liquid depositing one or more zinc oxide precursor compositions and forming at least one semiconductor layer of the electronic device comprising predominately amorphous zinc oxide from the liquid deposited one or more zinc oxide precursor compositions.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: July 17, 2012
    Assignee: Xerox Corporation
    Inventors: Yiliang Wu, Yuning Li, Beng S. Ong
  • Patent number: 8212296
    Abstract: Disclosed herein is a semiconductor device having a vertical MOS transistor having a channel of a first conductivity type and formed by burying a gate electrode in a semiconductor substrate, a planar MOS transistor having a channel of the first conductivity and having a gate electrode formed on the semiconductor substrate, and a planar MOS transistor having a channel of a second conductivity and having a gate electrode formed on the semiconductor substrate, the semiconductor device, including other circuit element(s), other than a transistor, formed either below or above the vertical MOS transistor having the channel of the first conductivity type.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Sony Corporation
    Inventors: Shuji Manda, Hiroshi Takahashi
  • Patent number: 8211758
    Abstract: It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 3, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo
  • Patent number: 8207032
    Abstract: Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 ?/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, Sanh D. Tang
  • Patent number: 8138039
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Robert J. Burke, Anand Srinivasan
  • Patent number: 8119471
    Abstract: A method for manufacturing a semiconductor device including a vertical double-diffusedmetal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8105890
    Abstract: A method of forming a semiconductor structure comprises forming a first layer of silicon and then forming a second, silicon germanium, layer adjacent the silicon layer. A thin third layer of silicon is then formed adjacent the second layer. A gate structure is then formed upon the third layer of silicon using convention Complementary Metal Oxide Semiconductor processes. Trenches are then formed into the second layer and the structure is then exposed to a thermal gaseous chemical etchant, for example heated hydrochloric acid. The etchant removes the silicon germanium, thereby forming a Silicon-On-Nothing structure. Thereafter, conventional CMOS processing techniques are applied to complete the structure as a Metal Oxide Semiconductor Field Effect Transistor, including the formation of spacer walls from silicon nitride, the silicon nitride also filling a cavity formed beneath the third layer of silicon by removal of the silicon germanium.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Terry Sparks
  • Patent number: 8093122
    Abstract: A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: January 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chun-Hee Lee
  • Patent number: 8004049
    Abstract: A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jean-Michel Reynes, Stephane Alves, Ivana Deram, Blandino Lopes, Joel Margheritta, Frederico Morancho
  • Patent number: 7960761
    Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 14, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Woong Chung, Sang Don Lee
  • Patent number: 7943459
    Abstract: A semiconductor device is provided with a conductor wire and a fuse wire formed in an insulating film over a semiconductor substrate, a first under-pad-wire insulating film formed above the insulating film, a second under-pad-wire insulating film formed on the first under-pad-wire insulating film, a pad wire formed in an area above the conductive wire, in the first and second under-pad-wire insulating films and an opening formed by leaving a part of the first under-pad-wire insulating film in an area above the fuse wire, in the first and second under-pad-wire insulating films, wherein the second under-pad-wire insulating film comprises an element different from that of the first under-pad-wire insulating film.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Akiyama, Takaya Matsushita
  • Patent number: 7936569
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7879676
    Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: February 1, 2011
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
  • Patent number: 7858478
    Abstract: A method for producing an integrated circuit including a trench transistor and an integrated circuit is disclosed.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: December 28, 2010
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 7851293
    Abstract: A method for forming a vertical channel transistor in a semiconductor device includes providing a substrate, forming pillar patterns extending perpendicular from the upper surface of the substrate, forming a spin on carbon (SOC) layer in a gap region between the pillar patterns, forming photoresist patterns above a resultant structure where the SOC layer is filled to expose a region for an isolation trench, etching the SOC layer between the photoresist pattern barriers to expose the region for the isolation trench, and etching the exposed structure to a certain depth forming the isolation trench.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: December 14, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun-Seok Cho
  • Publication number: 20100308385
    Abstract: Disclosed herein is a semiconductor device having a vertical MOS transistor having a channel of a first conductivity type and formed by burying a gate electrode in a semiconductor substrate, a planar MOS transistor having a channel of the first conductivity and having a gate electrode formed on the semiconductor substrate, and a planar MOS transistor having a channel of a second conductivity and having a gate electrode formed on the semiconductor substrate, the semiconductor device, including other circuit element(s), other than a transistor, formed either below or above the vertical MOS transistor having the channel of the first conductivity type.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 9, 2010
    Applicant: Sony Corporation
    Inventors: Shuji Manda, Hiroshi Takahashi
  • Patent number: 7824982
    Abstract: The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The substrate is etched to form a plurality of trenches and cross-trenches which define a plurality of pillars. After the etching, dopant is implanted within the trenches to form a source/drain region that extends less than an entirety of the trench width. The invention includes a semiconductor construction having a bit line disposed within a semiconductor substrate below a first elevation. A wordline extends elevationally upward from the first elevation and substantially orthogonal relative to the bit line. A vertical transistor structure is associated with the wordline. The transistor structure has a channel region laterally surrounded by a gate layer and is horizontally offset relative to the bit line.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20100264496
    Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 21, 2010
    Applicant: COMM. A L'ENERGIE ATOM. ET AUX ENERGIES ALTERNA
    Inventors: Olivier Thomas, Thomas Ernst
  • Patent number: 7816229
    Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 19, 2010
    Assignee: Infineon Technologies Austria AG
    Inventor: Franz Hirler
  • Patent number: 7808039
    Abstract: A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Jeffrey B. Johnson, Tak H. Ning, Robert R. Robison
  • Patent number: 7803677
    Abstract: A method of manufacturing a semiconductor device, particularly a vertical transistor, including forming a contact hole and forming a pillar using an epitaxial growth process.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheol Kyun Kim
  • Patent number: 7786528
    Abstract: A trench MOSFET with improved metal schemes is disclosed. The improved contact structure applies a buffer layer to minimize the bonding damage to semiconductor when bonding copper wire upon front source and gate metal without additional cost.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: August 31, 2010
    Assignee: Force MOS Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 7767526
    Abstract: Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: August 3, 2010
    Assignee: Alpha & Omega Semiconductor Incorporated
    Inventors: Yeeheng Lee, Hong Chang, Tiesheng Li, John Chen, Anup Bhalla
  • Patent number: 7642154
    Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Kwang Young Ko
  • Patent number: 7615449
    Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Woong Chung, Sang Don Lee