Abstract: Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in a surface of the substrate adjacent to the trench region and in contact with the channel region, and gate electrodes at sides of the trench insulated from the trench wall.

Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.

Abstract: A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.

Abstract: A surface of a semiconductor substrate is selectively etched to form a first opening, which serves as the opening of a trench. A USG film is deposited on the first opening. A second opening, the width of which is smaller than that of the first opening, is formed in the USG film within the first opening. An inner section of the trench is formed by etching while using the USG film as a mask. The inner surface of the inner region is thermally oxidized to form a silicon oxide film, and a gate insulating film is made by the silicon oxide film and the USG film. A gate electrode is formed in the trench. The gate insulating film is relatively thick at the opening of the trench, so the breakdown voltage at the opening of the trench is increased.

Abstract: Charge balancing is achieved in a compensation component by creating compensation regions having different thickness. In this manner, the ripple of the electric field can be chosen to have approximately the same magnitude in all of the compensation regions.

Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface and methods of making the same.

Abstract: A vertical semiconductor transistor component is built up on a substrate by using a statistical mask. The vertical semiconductor transistor component has vertical pillar structures statistically distributed over the substrate. The vertical pillar structures are electrically connected on a base side thereof to a first common electrical contact. The vertical pillar structures include, along the vertical direction, layer zones of differing conductivity, and have insulation layers on their circumferential walls. An electrically conductive material is deposited between the pillar structures and forms a second electrical contact of the semiconductor transistor component. The pillar structures are electrically contacted to a third common electrical contact on their capping side.

Abstract: A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium, thallium and/or palladium, in a cluster-like manner inside an n-conductive region.

Abstract: A semiconductor device constituting an IGBT exhibits low losses yet can be manufactured using an inexpensive wafer and with high yields, and exhibits low losses. The IGBT is produced by using a wafer, for example an FZ wafer, that is cut form an ingot and has its surface polished and cleaned, wherein an n-type impurity diffusion layer having an enough dose to stop the electric field in turn-off is provided between a collector layer and a base layer as a field-stop layer for stopping an electric field in turn-off. The thickness of this field-stop layer defined by Xfs-Xj is controlled in the range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer is twice the impurity concentration of the base layer, and Xj is the position of the junction between the filed-stopping layer and the collector layer.

Abstract: An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches.

Abstract: The present invention provides high voltage MOS transistors that have a high breakdown voltage and a low specific ON resistance in the drain. High voltage MOS transistors of the present invention include a source region and a drain region formed in an body region. The drain region includes a low doped extension region, a higher doped base region, and a more highly doped type region. The extension region of the drain extends toward the gate, further than the base region. The extension region increases the breakdown voltage in the drain near the gate where the electric field is high, because it has relatively low doping concentration. The base region also increases the breakdown voltage between the drain and the body because the base region has a lower doping concentration than the region.

Abstract: A field transistor for electrostatic discharge (ESD) protection and method for making such a transistor is described. The field transistor includes a gate conductive layer pattern formed on a field oxide layer. Since the gate conductive layer pattern is formed on the field oxide layer, a thin gate insulating layer having a high possibility of insulation breakdown is not used. To form an inversion layer for providing a current path between source and drain regions, a field oxide layer is interposed to form low concentration source and drain regions overlapped by the gate conductive layer pattern.

Abstract: A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region.

Abstract: A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

Abstract: A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

Abstract: A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.

Abstract: For fabricating a vertical field effect transistor on a semiconductor substrate, a first layer of dielectric material is deposited on the semiconductor substrate. A layer of metal is then deposited on the first layer of dielectric material, and a second layer of dielectric material is deposited on the layer of metal. A channel opening is etched through the second layer of dielectric material, the layer of metal, and the first layer of dielectric material. A source and drain dopant is implanted through the channel opening and into the semiconductor substrate to form a drain region of the vertical field effect transistor in the semiconductor substrate. Metal oxide is then formed at any exposed surface of the layer of metal on sidewalls of the channel opening in a thermal oxidation process to form a gate dielectric of the vertical field effect transistor.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.

Abstract: A nonvolatile semiconductor memory, including a ferroelectric capacitor connected to the gate of a MOSFET, comprises a silicon thin film formed in stripes on an insulated substrate and having an n+-region, a p-region and an n+-region layered in its thickness direction, a hole formed in a portion of the silicon thin film and extending to the lower n+-region, a gate electrode provided on the side walls of the hole with a gate insulting film interposed therebetween, and a ferroelectric capacitor formed on the silicon thin film and having its lower electrode connected to the gate electrode.

Abstract: An improved structure and method are provided for signal processing. The structure includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The body region of the dual-gated MOSFET is a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.

Abstract: A low-power-loss power semiconductor switching device and its fabricating method are proposed to provide a low-power-loss IGBT, MCT, or GTO with a voltage rating of less than 2 kV, wherein said device includes a combination of an ultra-thin lightly-doped back-side p+ emitter formed by ion implanting and a nonuniformly-doped n-type base layer which contains a residual layer of a priorly-diffused n+ layer on one side. And in accordance with said method, the residual diffused-layer near the p+ emitter contained in the nonuniformly doped base is formed in the first step of the fabricating process before the thinning of the substrate. After the thinning of the substrate, only low-temperature processes occur. This invention combines the feature of low on-voltage of a PT-IGBT and the feature of short switching time of an NPT-IGBT, and is very applicable to practical manufacturing.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

Abstract: A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, and the barrier layer prevent the dopants from diffusing into the upper horizontal surface.

Abstract: The present invention improves the characteristic of a trench-type vertical MOSFET. When a trench 23 serving as a gate 25 is formed, it is made in a shape of “&ggr;” which is convex toward the inside of the trench. Thus, the surface area of the trench is reduced so that both gate-source capacitance and gate-drain capacitance can be reduced, thereby shortening the switching time of the MOSFET.

Abstract: A buried gate type power field effect transistor has a drain layer forming a lower part of a silicon substrate, a base layer forming another part of the silicon substrate on the lower part, a source region forming a surface portion of the silicon substrate on the another part, a gate insulating layer covering an inner surface of a groove penetrating from the surface of the silicon substrate through the source region and the base region into the drain region and a polysilicon gate electrode filling the secondary groove defined by the gate insulating layer, wherein the gate electrode is formed with a recess exposed to the upper surface thereof and covered with an insulating layer defining a secondary recess filled with a piece of polysilicon so as to reduce the effective width of the gate electrode, thereby creating the upper surface substantially coplanar with the surface of the source region in spite of an etch back carried on a polysilicon layer for forming the gate electrode.

Abstract: A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: A vertical double diffuses MOSFET includes a nitride film (26) formed on a gate electrode (18). An ion implant window (34) is formed through the nitride film. P-type ions are implanted through the ion implant window into the semiconductor substrate (12), and the implanted ions are diffused to thereby form a main diffusion region (14). At the same time, the oxide film is grown inside the ion implant window to form a thick walled portion (36). Ions of the p-type are implanted through, as a mask, the thick walled portion, gate electrode and nitride film into semiconductor substrate, and thermally diffused thus forming a channel diffusion region (22). Further, n-type ions are implanted through the same mask and then thermally diffused to provide source diffusion regions.

Abstract: Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

Abstract: A trench field-effect transistor with a self-aligned source. At least a portion of the source implantation dose (604) is implanted underneath the gate (610) of a trench transistor by implanting an a non-orthogonal angle to the sidewall (608) of the trench. In one embodiment, a slow diffuser, such as arsenic, is implanted to minimize the post-implant diffusion. The resulting structure ensures gate-source overlap, and a consistent, small, gate-source capacitance with a lower thermal budget for the resultant device. The narrow depth of the source, in conjunction with its unique L-shape, improves device ruggedness because the source doping does not compensate the heavy body doping as much as with conventional devices. In one embodiment, the substrate is rotated 180 degrees within the implanter to implant both sidewalls of a trench.

Abstract: An electro-static discharge (ESD) circuit of a semiconductor device, a structure thereof and a method for fabricating the ESD structure are provided. In the ESD circuit, a gate electrode and a drain region of a MOS transistor are connected to an electrical signal pad, and a Zener diode is connected to a source region of the MOS transistor. A threshold voltage of the MOS transistor is higher than an operating voltage of an internal circuit and lower than a drain junction breakdown voltage of a MOS transistor constituting the internal circuit. Also, instead of using a Zener diode for each signal pad, a common diode having a maximized junction area can be shared by a plurality of signal pads.

Abstract: This specification disclosed a multilayer film structure of a tunneling magneto-resistor and the manufacturing of the same, the structure being able to increase the tunneling magneto-resistance (TMR) ratio and to decrease the difficulty in manufacturing. The multilayer film structure disclosed herein forms, in a three-layer film structure composed of two layers of ferromagnetic films and an insulating layer provided in between, a layer of moderately thick ferromagnetic metal insertion between one of the ferromagnetic film and the insulating layer. Through the insertion the tunneling magneto-resistance ratio can be greatly increased and the thickness of the insulating layer is increased to the range where the manufacturing difficulty is lowered.

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body with a gate electrode (2) which is arranged in a trench between a source region (3) and a drain region (4), which are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode there is an oxide-nitride-oxide layer sequence (5, 6, 7), which is provided for the purpose of trapping charge carriers at source and drain.

Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution.

Abstract: A lateral MOS gate semiconductor device including Zener diodes has a structure in which the Zener diodes are integrated within the device. The Zener diodes are connected in parallel to a parasitic diode within the device, between drain and source terminals, and have a relatively low breakdown voltage. Accordingly, when a large reverse voltage is applied due to an avalanche energy generated by an inductive load upon turning off the device, breakdown occurs in the Zener diodes before the internal parasitic diode, thus allowing reverse current to flow from the drain terminal to the source terminal through the Zener diodes. As described above, the reverse current flows through the Zener diodes, rather than through the parasitic diode, so that a parasitic bipolar junction transistor is prevented from being turned on. Therefore, the device can endure a high avalanche energy.

Abstract: A transistor (30) uses a single continuous base region (40) with an undulating structure. The semiconductor device is an insulated gate field effect transistor having a semiconductor substrate with a plurality of doped base branches, which extend into the semiconductor substrate, form into a single base region for the entire transistor. Each of the plurality of base branches (82) is undulating and of substantially constant width, and each of the base branches undulates in-phase with the immediately adjacent base branches. A continuous gate layer (34) overlies the semiconductor substrate and is self-aligned to the plurality of base branches. The undulating structure of the base region improves channel density, and thus lowers on-resistance, and the use of a single base region ensures that all portions of the base region throughout the device will be at a substantially constant electric potential.

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract: A method and system for providing a contact in a semiconductor device including a plurality of gates is disclosed. The method and system include providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact within the insulating layer. The at least one contact has a reduced width that is less than approximately 0.

Abstract: A trench MOSFET device and process for making the same are described.

Abstract: The invention is directed to a semiconductor component having a semiconductor body with two principal faces, at least two electrodes at least one electrode being provided on a principal face, and zones of a conductivity type opposite one another that are arranged in alternation in the semiconductor body and extend perpendicularly to the two principal faces. For an application of a voltage to the two electrodes, the zones arranged in alternation mutually clear of charge carriers so that an essentially constant field strength is built up in the semiconductor body between the two electrodes These zones arranged in alternation inventively contain at least one cavity that is preferably closed by a glass layer.

Abstract: An insulated-gate semiconductor element with a trench structure is provided, which has a high breakdown voltage even though a silicon carbide substrate is used that is preferable to obtain a semiconductor element with favorable properties. The surface of a silicon carbide substrate is etched to form a concave portion. Then, a particle beam, for example an ion beam, is irradiated from above, and a defect layer is formed at least in a bottom surface of the concave portion. The substrate is heated in an oxidation atmosphere, and an oxide film is formed at least on a side surface and the bottom surface of the concave portion. Then, a gate electrode is formed on the oxide film.

Abstract: The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.

Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.

Abstract: A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.