Abstract: An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Abstract: A semiconductor device causing no malfunction and having high ESD resistance against all cases of surges as well as a method of manufacturing the same are obtained.

Abstract: An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: In a semiconductor device having a fuse and an etching stopper film covering the fuse, an optical window exposing the etching stopper film and a contact hole exposing a conductor pattern are formed simultaneously. By applying a dry etching process further to the etching stopper film, an insulation film covering the fuse is exposed in the optical window.

Abstract: There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the copper fuse layer from material whose light absorption coefficient is greater than that of a copper wiring layer. Light absorbed by the light absorbing layer is transmitted, through heat conduction, to the copper wiring layer beneath the light absorbing layer and further to a barrier metal layer beneath the copper wiring layer. Even when the widely-used conventional laser beam of infrared wavelength is used, the copper fuse can be blown. Since a guard layer is formed below the fuse layer, there can be prevented damage to the silicon substrate, which would otherwise be caused by exposure to the laser beam of visible wavelength.

Abstract: A method of forming nano-scale features with conventional multilayer structures, and nano-scale features formed thereby. The method generally entails forming a multilayer structure that includes a polycrystalline layer and at least one constraining layer. The multilayer structure is patterned to form first and second structures, each of which includes the polycrystalline and constraining layers. At least the first structure is then locally heated, during which time the constraining layer restricts the thermal expansion of the polycrystalline layer of the first structure. As a result, stresses are induced in the polycrystalline layer of the first structure, causing substantially two-dimensional grain growth from the edge of the first structure. Sufficient grain growth occurs to produce a third structure which, based on the grain size of the polycrystalline layer, will be a nano-scale structure.

Abstract: In the fuse element structure of the semiconductor device, the first insulating film region is provided in a groove-like manner in the semiconductor substrate. Further, the fuse element is formed on the first insulating film region, and the second insulating film region is formed on the region on the fuse element and the first insulating film. The metal plug is connected to the fuse element, and the surface thereof is exposed to the surface of the second insulating film region. With this structure, the meltdown of the fuse by the laser blow is facilitated, and the area of the fuse is reduced. Thus, as the downsizing of the element is further advanced, it is possible to provide a fuse element structure capable of melting down a fuse without causing an affect on another fuse adjacent to the melted-down fuse with the scattering pieces thereof.

Abstract: A semiconductor device according to one embodiment may include protruding portions (2) formed on a periphery of a fuse pattern. Narrowed portions (3) are gaps between adjacent protruding portions (2), and may be filled with a first insulation layer (5), such as an oxide or the like. A silica layer (6) may then be deposited for enhancing the flatness of a semiconductor device surface. Excess silica layer (6) portions may be etched back and remaining silica layer (6) between fuses (1) may be planarized. A second insulation layer (7) may be formed that can contact portions of a first insulation layer (5) that fill narrowed portions (3). Consequently, the extents of a silica layer (6) may be interrupted along a periphery and between adjacent fuses by first insulation layer (5).

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: The semiconductor device comprises a blocking layer 12 formed on a substrate 10, an insulation film 14 formed on the blocking layer 12, and a fuse 22 formed on the insulation film 14. The blocking layer 12 is formed below the fuse 22, whereby the fuse is disconnected by laser ablation, and the laser ablation can be stopped by the blocking layer 12 with good controllability without damaging the substrate. The fuses to be disconnected can be arranged at a very small pitch, which can improve integration of the fuse circuit.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract: The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5 nanowatts. The cell structure allows an SRAM cell to be fabricated in only a 16 feature-square area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of two bus bars of minimum feature size width, each of which has a tunnel diode implanted therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also provided.

Abstract: An anti-fuse for programming a redundancy cell and a repair circuit having a programming apparatus are disclosed.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optionally, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, to be used with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the amorphous silicon layer protected by a thin barrier layer, during the patterning procedure. The protected antifuse layer results in a reproducible thickness, and thus reproducible pulsing voltages, needed for rupturing of the antifuse layer. Planarization of an underlying metal plug, via a conductor layer refill procedure, offers a smooth top surface, flush with the top surface of the adjacent interlevel dielectric layer, for the overlying antifuse layer.

Abstract: A structure and method of fabricating a metallization fuse line is disclosed. The structure can be formed on a semiconductor substrate, including an insulator structure formed on the substrate, the insulator structure having an upper layer and a lower layer, the upper being thinner than the lower, the insulator structure having a plurality of openings of varying depth, and a metal structure inlaid in the insulator structure, the metal structure having first and second portions and a third portion there between that is substantially more resistive than the first and second portions, the third portion having a thickness substantially similar to the thickness of the upper layer of the insulator structure. The upper layer includes a nitride, the lower layer includes an oxide and the metal structure includes copper. The fuse structure allows formation of “easy to laser delete” thin metal fuses within segments of thick metal lines.

Abstract: A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. In an example embodiment, a fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existing mask of the last metal interconnect layer, typically the pad mask. The passivation layer on top of the bond pads is opened to expose the bonding pads. At the same time, a residual oxide window is defined over the fuse. The residual oxide covering the fuse provides for a reliable and reproducible fuse.

Abstract: A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via.

Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

Abstract: A fusible link in an integrated semiconductor circuit and a process for producing the fusible link contemplate the disposition of a fusible link, which is constructed with a cross-sectional constriction as a desired fusing point for its conductor track, in a void. A surface of the void and/or a bare conductor track can be covered with a protection layer, to prevent corrosion. The advantages of such a fusible link are a lower ignition energy and increased reliability. The fusible link may be used as a memory element of a PROM.

Abstract: A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is coupled to a substrate and the second via plug is coupled to the well. These two via plugs are further coupled by a conductive bridge so that both the well and the substrate have the same voltage.

Abstract: The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window area. A cap layer 38 and an interlevel dielectric layer (ILD) 40 are formed over the fuse structure. A first annular ring 44 (e.g., contact w-plug) is formed over the isolation region 20 surrounding the fuse window area 30 and over the fuse structure 32 33 34. A key feature is that the first annular ring 44 and the cap layer 38 form a moisture proof seal over the fuse structure. A first conductive wiring line 48 is formed over the first annular ring 44. Next, an inter metal dielectric (IMD) layer 50 is formed over the interlevel dielectric layer 40. A second annular ring 52 is formed through the inter metal dielectric layer 50 on the first conductive wiring line 48.

Abstract: A method and apparatus for fast electronic self-destruction of a CMOS integrated circuit. The present invention electrically destroys devices containing semiconductor components, securing the components from inspection by detecting the initiation of an attempt to inspect the component and, responsive thereto, electrically destroying the component. In some embodiments of the present invention, a switcheable pad having a destruct state and an operating state is connected to a well or to the substrate of the semiconductor device. When in destruct state, the switcheable pad drives the voltage of the well or substrate to a voltage that induces latch-up of the semiconductor device, allowing very large currents to flow through active or passive elements fabricated on the surface of the semiconductor device.