Total Dielectric Isolation Patents (Class 438/219)
  • Patent number: 7510926
    Abstract: A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 31, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann
  • Patent number: 7485521
    Abstract: Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: February 3, 2009
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)
    Inventors: Huilong Zhu, Brian L. Tessier, Huicai Zhong
  • Patent number: 7396715
    Abstract: Patterning is performed in such a manner that an end portion fabricated of a second gate insulating film partially overlaps an end portion fabricated of a first gate insulating film. Then, a surface recovery treatment is performed in the aforementioned state where the first and second gate insulating films partially overlap each other.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 8, 2008
    Assignee: Fujitsu Limited
    Inventor: Kazuto Ikeda
  • Publication number: 20070278593
    Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.
    Type: Application
    Filed: May 24, 2007
    Publication date: December 6, 2007
    Inventor: Takeshi Watanabe
  • Patent number: 7279769
    Abstract: To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an element isolation trench located between the element formation regions and having an element isolation insulating film embedded therein, and a gate insulating film, a gate electrode and a plurality of interconnect layers formed thereabove, each formed in the element formation region, wherein the element isolation trench has a thermal oxide film formed between the semiconductor substrate and the element isolation insulating film, and the element isolation film has a great number of micro-pores formed inside thereof and is more porous than the thermal oxide film.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Norio Ishitsuka, Jun Tanaka, Tomio Iwasaki, Hiroyuki Ohta
  • Patent number: 7262486
    Abstract: The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device formation region A1 of the SOI substrate 1. The through electrode 40 reaches the insulating layer 20 from the silicon layer 30. Specifically, the through electrode 40 extends to an inner part of the insulating layer 20 originating from a surface of the silicon layer 30 while penetrating the silicon layer 30. Here, an end face 40a of the through electrode 40 at the insulating layer 20 side stops inside the insulating layer 20.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 28, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Masaya Kawano, Tsutomu Tashiro, Yoichiro Kurita
  • Patent number: 7253068
    Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, Srinath Krishnan, Mario Pelella
  • Patent number: 7247543
    Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: July 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiaw-Ren Shih, Jian-Hsing Lee, Shui-Hung Chen
  • Patent number: 7235460
    Abstract: A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional); the other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: June 26, 2007
    Assignee: STMicroelectronics, Inc.
    Inventor: Jia Li
  • Patent number: 7205190
    Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: April 17, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masao Okihara
  • Patent number: 7202125
    Abstract: A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: April 10, 2007
    Assignee: SanDisk Corporation
    Inventors: Tuan Pham, Masaaki Higashitani
  • Patent number: 7189606
    Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, John K. Zahurak
  • Patent number: 7172914
    Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: February 6, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventor: Sundar Narayanan
  • Patent number: 7135365
    Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: November 14, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Cheng Liu, Wen-Chi Chen, Tzu-Yun Chang, Bang-Chiang Lan, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
  • Patent number: 7115463
    Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Devendra K. Sadana, Dominic J. Schepis, Michael D. Steigerwalt
  • Patent number: 7075149
    Abstract: A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semico
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shingo Sato, Atsuko Yamashita, Hideki Okumura, Kenichi Tokano
  • Patent number: 7060549
    Abstract: SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: June 13, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Craig, Karsten Wieczorek, Manfred Horstmann
  • Patent number: 7052948
    Abstract: The invention relates to a film or a layer made of semi-conducting material with low defect density in the thin layer, and a SOI-disk with a thin silicon layer exhibiting low surface roughness, defect density and thickness variations. The invention also relates to a method for producing a film or a layer made of semi-conductive material. Said method comprises the following steps: a) producing structures from a semi-conductive material with periodically repeated recesses which have a given geometrical structure, b) thermally treating the surface structured material until a layer with periodically repeated hollow spaces is formed under a closed layer on the surface of the material, c) separating the closed layer on the surface along the layer of hollow spaces from the remainder of the semi-conductive material.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 30, 2006
    Assignee: Siltronic AG
    Inventors: Brian Murphy, Reinhold Wahlich, Rüdiger Schmolke, Wilfried Von Ammon, James Moreland
  • Patent number: 7053451
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: May 30, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7049677
    Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: May 23, 2006
    Assignee: Power-One, Inc.
    Inventors: Badredin Fatemizadeh, Ali Salih
  • Patent number: 7022565
    Abstract: A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric layer, and the upper electrode layer are formed in sequence in a plurality of shallow trench isolation regions to form a trench capacitor. The present invention uses a trench capacitor to substitute for the 3-dimensional structure capacitor to overcome the disadvantages of the conventional capacitor, resulting in increasing the surface area of electrode and the capacitance.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: April 4, 2006
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventor: Jung-Cheng Kao
  • Patent number: 7005342
    Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Jigish D. Trivedi
  • Patent number: 6977204
    Abstract: The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing an increase of contact resistance caused by a decrease in dopant concentration and suppressing diffusions of dopants implanted into the contact. The dopants are doped in a manner to allow the conductive layer to have different doping distributions with respect to a thickness. Particularly, the dopants are doped until reaching a target deposition thickness by gradually increasing a concentration of the dopants from a first concentration to a second concentration for an interval from an initial deposition of the conductive layer to the target deposition thickness, and the second concentration is consistently maintained throughout for an interval from the target deposition thickness to a complete deposition thickness.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: December 20, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Jae Joo
  • Patent number: 6964883
    Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: November 15, 2005
    Assignee: Industrial Technology Research Institute
    Inventor: Chyh-Yih Chang
  • Patent number: 6958266
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: October 25, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6955957
    Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: October 18, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Patent number: 6921688
    Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 26, 2005
    Assignee: Alliance Semiconductor
    Inventor: Ritu Shrivastava
  • Patent number: 6900108
    Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: May 31, 2005
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Alexander A. Ned
  • Patent number: 6887772
    Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: May 3, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dae Woo Lee, Tae Moon Roh, Yil Suk Yang, Il Yong Park, Byoung Gon Yu, Jong Dae Kim
  • Patent number: 6876054
    Abstract: An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a first conductive channel, a second conductive channel and an isolation layer. The isolation layer is formed from and over the first conductive channel, interposing the first conductive channel and the second conductive channel and configured both to isolate the second conductive channel electrically from the first conductive channel and transfer momentum between charge carriers in the first conductive channel and charge carriers in the second conductive channel.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: April 5, 2005
    Assignee: Agere Systems Inc.
    Inventors: Shye Shapira, William B. Wilson, Gerard Zaneski
  • Patent number: 6867086
    Abstract: High density plasma chemical vapor deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots are provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. The etch back part of the process involves an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality gap fill operations.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: March 15, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Robert A. Shepherd, Jr., Vishal Gauri, George D. Papasouliotis
  • Patent number: 6830977
    Abstract: A method of forming an isolation trench in a semiconductor includes forming a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. The method also includes forming a second isolation trench portion within and extending below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: December 14, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Keiji Jono, Hirokazu Ueda, Hiroyuki Watanabe
  • Publication number: 20040217429
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Application
    Filed: May 25, 2004
    Publication date: November 4, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Publication number: 20040217428
    Abstract: Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insulation layer is formed on the isolation layer and on a portion of the active region neighboring the isolation layer. A silicide layer is formed on source/drain regions between the blocking insulation layer and the sidewall spacers. Some embodiments include defining an active region of a substrate using an isolation layer, forming a gate pattern on the active region, implanting impurities into the active region, and forming a spacer insulation layer on a surface of the substrate with the gate pattern. A region of the spacer insulation layer becomes thinner the closer it is to the gate pattern. Other embodiments are described in the claims.
    Type: Application
    Filed: January 2, 2004
    Publication date: November 4, 2004
    Inventors: Jeong-Min Choi, Tae-Hong Ha
  • Patent number: 6809014
    Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 26, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Jigish D. Trivedi
  • Publication number: 20040173867
    Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Inventor: Kurt D. Beigel
  • Patent number: 6777770
    Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure that includes a vapor-deposited dielectric material. The dielectric material has a predetermined microstructure formed using a glancing angle deposition (GLAD) process. The microstructure includes columnar structures that provide a porous dielectric material. One aspect is a method of forming a low-k insulator structure. In one embodiment, a predetermined vapor flux incidence angle &thgr; is set with respect to a normal vector for a substrate surface so as to promote a dielectric microstructure with individual columnar structures. Vapor deposition and substrate motion are coordinated so as to form columnar structures in a predetermined shape. Other aspects are provided herein.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: August 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6777772
    Abstract: Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Taya, Takio Ohno, Naofumi Murata
  • Patent number: 6767781
    Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: July 27, 2004
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Larry A. Nesbit, Jonathan E. Faltermeier, Ramachandra Divakaruni, Wolfgang Bergner
  • Patent number: 6764921
    Abstract: A semiconductor device of the present invention includes a MISFET provided in an element formation region Re of a semiconductor substrate 11 and a trench isolation 13 surrounding the sides of the element formation region Re. An oxygen-passage-suppression film 23 is provided from the top of the trench isolation 13 to the top of a portion of the element formation region Re adjacent to the trench isolation 13. The oxygen-passage-suppression film 23 is made of a silicon nitride film or the like through which oxygen is less likely to permeate. Therefore, since it becomes hard that the upper edge of the element formation region Re of the semiconductor substrate 11 is oxidized, an expansion of the volume of the upper edge is suppressed, thereby reducing a stress.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Imade, Hiroyuki Umimoto
  • Patent number: 6764892
    Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: July 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo
  • Patent number: 6750116
    Abstract: The present invention provides a method for making an asymmetric inner structure in a contact or trench having a first sidewall, second sidewall, and a bottom in a semiconductor layer. A conformal dielectric layer is deposited on the interior surface of the contact or trench covering the first sidewall, second sidewall, and the bottom. A title angle ion implantation process is carried out to implant ions into the dielectric layer on the first sidewall and the bottom, but not the dielectric layer on the second sidewall. Thereafter, the doped dielectric layer on the first sidewall and the bottom is selectively etched away and leaving the un-doped dielectric layer on the second sidewall intact.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: June 15, 2004
    Assignee: Nanya Technology Corp.
    Inventor: Yinan Chen
  • Patent number: 6734524
    Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 11, 2004
    Assignee: Motorola, Inc.
    Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose, Todd Roggenbauer, Paul Hui
  • Patent number: 6716691
    Abstract: A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: April 6, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: David R. Evans, Sheng Teng Hsu, Bruce D. Ulrich, Douglas J. Tweet, Lisa H. Stecker
  • Patent number: 6706580
    Abstract: A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: March 16, 2004
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Koichi Hashimoto
  • Publication number: 20030230786
    Abstract: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 18, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-Young Kim, Ki-Nam Kim
  • Patent number: 6639296
    Abstract: In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: October 28, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Koido, Riichiro Shirota, Hirohisa Iizuka
  • Patent number: 6633073
    Abstract: Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and forms a depletion region at the junction with the p-type substrate. The depth and width of the depletion region is dependent on the doping concentration of the deep n-well and the amount of reverse bias voltage applied to the deep n-well. In general, a wider and deeper depletion region may be formed by more heavily doping the deep n-well and applying a higher reverse bias voltage. By properly constructing the deep n-well and applying a high reverse bias voltage, a deep and wide depletion region may be formed to provide a barrier against noise from entering the quiet region.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: October 14, 2003
    Assignee: RF Micro Devices, Inc.
    Inventors: Ali Rezvani, Douglas Sudjian
  • Patent number: 6603174
    Abstract: An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral portion of the SOI layer (3) is a silicon oxide film (6), the side surface (6H) of which is integrally joined to the side surface (8H) of the silicon oxide film (8). The thickness of the peripheral portion of the SOI layer (3) decreases as closer to the end portion (3H) of the SOI layer (3), while the thickness of the silicon oxide film (6) formed on the peripheral portion of the SOI layer (3) increases as closer to the end portion (3H). A gate oxide film (9) is formed on a predetermined region of the surface of the SOI layer (3), and joined to the silicon oxide film (6) at its end portion.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shoichi Miyamoto, Yuuichi Hirano, Takashi Ipposhi
  • Patent number: 6576959
    Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: June 10, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, Charvaka Duvvury, Hisashi Shichijo