Including Isolation Structure Patents (Class 438/218)
  • Patent number: 10157916
    Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Victor Chiang Liang, Chi-Feng Huang, Chia-Chung Chen, Chun-Pei Wu, Fu-Huan Tsai, Chung-Hao Chu Chu, Chin-Nan Chang, Ching-Yu Yang, Ankush Chaudhary
  • Patent number: 9647086
    Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 9, 2017
    Assignees: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven Bentley, Jody Fronheiser, Xin Miao, Joseph Washington, Pierre Morin
  • Patent number: 9559058
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 31, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Patent number: 9312389
    Abstract: Systems and methods are provide to achieve undoped body bulk silicon based devices, such as field effect transistors (FETS) and Fin Field Effect Transistors (FinFETs). In an embodiment, an epitaxial growth technique is used to form the silicon of an active region of a fin of a FinFET once a punchthrough stop (PTS) layer has been formed. In an embodiment, the epitaxial growth technique according to embodiments of the present disclosure produces a fin with a small notch in the active region.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 12, 2016
    Assignee: Broadcom Corporation
    Inventors: Shom Ponoth, Hemant Vinayak Deshpande
  • Patent number: 9299618
    Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Patent number: 9202751
    Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: December 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Andy Chih-Hung Wei, Guillaume Bouche, Mark A. Zaleski, Tuhin Guha Neogi, Jason E. Stephens, Jongwook Kye, Jia Zeng
  • Patent number: 9093533
    Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 9070771
    Abstract: A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9064799
    Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Hung-Jen Liao, Li-Chun Tien
  • Patent number: 9041116
    Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Steven J. Holmes, Ali Khakifirooz, Pranita Kulkarni, Shom Ponoth, Raghavasimhan Sreenivasan, Stefan Schmitz
  • Publication number: 20150140749
    Abstract: A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventor: Ki-chul KIM
  • Patent number: 9035379
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
  • Publication number: 20150115367
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first mask on a substrate; defining a first doped region through an opening of the first mask; forming a second mask on the first mask and filling in the opening of the first mask with the second mask; defining a second doped region through an opening of the second mask; and stripping the first mask and the second mask from the substrate. The present disclosure provides a semiconductor structure, including a substrate having a top surface; a first doped region having a first surface; and a second doped region having a second surface. The first surface and the second surface are coplanar with the top surface of the substrate. Either of the doped regions has a monotonically decreasing doping profile from the top surface of the substrate to a bottom of the doped region.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: CHUN-MING LIN, CHIU-HUA CHUNG, YU-SHINE LIN, BOR-WEN LAI, TSUNG-LIN LEE
  • Publication number: 20150118807
    Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).
    Type: Application
    Filed: November 25, 2014
    Publication date: April 30, 2015
    Inventors: Ming-Hsi YEH, Hsien-Hsin LIN, Ying-Hsueh CHANG CHIEN, Yi-Fang PAI, Chi-Ming YANG, Chin-Hsiang LIN
  • Publication number: 20150111351
    Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 23, 2015
    Applicant: IMEC VZW
    Inventors: Min-Soo Kim, Guillaume Boccardi, Soon Aik Chew, Naoto Horiguchi
  • Patent number: 9012285
    Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 21, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akihiro Usujima, Shigeo Satoh
  • Publication number: 20150102416
    Abstract: A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.
    Type: Application
    Filed: May 17, 2012
    Publication date: April 16, 2015
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zuozhen Fu, Qiuxia Xu, Dapeng Chen
  • Patent number: 8975132
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8975154
    Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 10, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Zahra Aitfqirali-Guerry, Yves Campidelli, Denis Pellissier-Tanon
  • Patent number: 8969149
    Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8969164
    Abstract: A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8962441
    Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Johannes M. van Meer
  • Patent number: 8962418
    Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hoshino
  • Publication number: 20150035069
    Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chien-Ting Lin, Po-Chao Tsao, Chung-Fu Chang, Cheng-Guo Chen
  • Patent number: 8941206
    Abstract: A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Andreas Meiser
  • Patent number: 8932920
    Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Russell T. Herrin, Laura J. Schutz, Steven M. Shank
  • Publication number: 20150011060
    Abstract: Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.
    Type: Application
    Filed: July 9, 2014
    Publication date: January 8, 2015
    Inventors: Nicolas Loubet, Balasubramanian Pranatharthiharan
  • Patent number: 8927438
    Abstract: Provided are methods for depositing a cerium doped hafnium containing high-k dielectric film on a substrate. The reagents of specific methods include hafnium tetrachloride, an organometallic complex of cerium and water.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Hyungjun Kim, Woo-Hee Kim, Min-Kyu Kim, Steven Hung, Atif Noori, David Thompson, Jeffrey W. Anthis
  • Patent number: 8928062
    Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoki Yasuda
  • Patent number: 8927362
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su
  • Patent number: 8921177
    Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8906760
    Abstract: Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 9, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Angelique Denise Raley
  • Publication number: 20140349451
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Application
    Filed: May 30, 2014
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Publication number: 20140339647
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 20, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Publication number: 20140339643
    Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.
    Type: Application
    Filed: May 17, 2013
    Publication date: November 20, 2014
    Applicant: International Busienss Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8889506
    Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 18, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 8871586
    Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 28, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Markus Lenski, Rolf Stephan
  • Publication number: 20140315362
    Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.
    Type: Application
    Filed: May 8, 2014
    Publication date: October 23, 2014
    Applicant: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Patent number: 8865539
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • Patent number: 8859377
    Abstract: A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Wayne Bather, Narendra Singh Mehta
  • Patent number: 8829616
    Abstract: A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony I-Chih Chou, Murshed M. Chowdhury, Arvind Kumar, Shreesh Narasimha
  • Patent number: 8828818
    Abstract: Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Mark S. Rodder
  • Patent number: 8823098
    Abstract: The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 2, 2014
    Assignee: Wuxi Versine Semiconductor Corp. Ltd.
    Inventors: Qin Huang, Yuming Bai
  • Patent number: 8815691
    Abstract: The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 8815674
    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Berthold Reimer, Markus Lenski, Bastian Haussdoerfer, Ardechir Pakfar
  • Patent number: 8803232
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
  • Patent number: 8790974
    Abstract: A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Nakai, Masato Suga, Jusuke Ogura
  • Patent number: 8790978
    Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Akihiro Usujima, Shigeo Satoh
  • Patent number: 8778754
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Su-Horng Lin