Abstract: An SOI substrate (30) comprises a buried oxide film (2), an SOI layer (3) formed on a first region (51) of the surface (2S) of the buried oxide film, and a silicon oxide film (8) formed on a second region (52) of the surface (2S). Formed on the peripheral portion of the SOI layer (3) is a silicon oxide film (6), the side surface (6H) of which is integrally joined to the side surface (8H) of the silicon oxide film (8). The thickness of the peripheral portion of the SOI layer (3) decreases as closer to the end portion (3H) of the SOI layer (3), while the thickness of the silicon oxide film (6) formed on the peripheral portion of the SOI layer (3) increases as closer to the end portion (3H). A gate oxide film (9) is formed on a predetermined region of the surface of the SOI layer (3), and joined to the silicon oxide film (6) at its end portion.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A method of reducing the aspect ratio for dry etch processes used to form contact hole and storage node openings in composite insulator layers, to expose regions of CMOS devices used for embedded memory cell applications, has been developed. The method features formation of CMOS devices for an embedded memory cell in a recessed region of a semiconductor substrate, while peripheral, higher performing CMOS devices are formed on a non-recessed, SOI layer. Removal of a top portion of a first planarized insulator layer, only in the embedded memory cell region, allows reduction of the aspect ratio of a storage node opening formed in the bottom portion of the first planarized insulator layer. Formation of an overlying, second planarized insulator layer results in a composite insulator layer comprised of a thinned, second planarized insulator layer on the underlying first planarized insulator layer, in the peripheral CMOS device region.

Abstract: A high voltage integrated switching device includes at least one high voltage switching circuit, preferably employing DMOS technology and characterized by a breakdown voltage of at least 100 volts, on a dielectrically isolated, bonded and vertically trenched silicon substrate. Multiple high-voltage switching circuits may be located in close proximity on a single substrate without circuit breakdown or shorting during circuit operation. The circuit may further include one or more low- and/or intermediate-voltage circuits employing, for example, CMOS and bipolar technologies on the same silicon substrate and located in close proximity without voltage breakdown during circuit operation.

Abstract: A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700° C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400° C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500° C.

Abstract: A method of isolating a CMOS device on a silicon on insulator substrate, wherein the substrate includes an insulating layer of top silicon formed thereon, includes growing a gate oxide layer on the top silicon layer; depositing a first layer of material on the gate oxide layer; removing the first layer of material, the gate oxide layer and the top silicon layer from a device field region; forming an insulating cup about the first layer of material, the gate oxide layer and the top silicon layer; depositing a second layer of material over the first layer of material and the insulating cup; etching the first layer of material and the second layer of material to form a gate electrode; implanting ions to form a source region and a drain region; passivating the structure; and metallizing the structure.

Abstract: A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.

Abstract: A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: A semiconductor device is provided in which a lowering in the breakdown voltage of a gate insulating film (nitrided silicon oxide film) in a boundary region between the upper-end corner portion of the side wall of an element isolating groove and a silicon substrate in the end portion of an element forming region which is formed in contact therewith can be suppressed without causing an increase in the number of steps (time for effecting the steps).

Abstract: Disclosed herein are various methods for preventing bending of a patterned SOI layer during trench sidewall oxidation, the methods comprising providing a patterned SOI layer having at least one trench, said patterned SOI layer disposed upon an underlying buried silicon oxide layer; and blocking diffusion of oxygen between said patterned SOI and buried silicon oxide layer.

Abstract: A circuit and method for an improved inverter is provided. The present invention capitalizes on a switched source impedance to prevent subthreshold leakage current at standby in low voltage CMOS circuits. The switched source impedance is provided by body contacted and backgated transistors. The gate and body of the transistors are biased to modify the threshold voltage of the transistors (Vt). This design provides fast switching capability for low power battery operated CMOS circuits and systems. The transistor structures offer the performance advantages from both metal-oxide semiconductor (MOS) and bipolar junction transistor (BJT) designs. The devices can be used in a variety of applications, digital and analog, wherever a more compact structure with low power consumption and fast response time is needed.

Abstract: The disclosed high voltage device includes a semiconductor substrate, and a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer buried within the semiconductor substrate. The high voltage device includes first and second drift regions formed over the second insulating layer in the semiconductor substrate and spaced apart from each other, an emitter impurity region formed in the first drift region, and a collector impurity region formed in the second drift region. The high voltage device further includes a second semiconductor layer adjacent to and insulated from the collector impurity region, and connected to the first semiconductor layer, and a third semiconductor layer adjacent to and insulated from the emitter impurity region, and connected to the first semiconductor layer.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: The claimed invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the claimed invention relates to a method of fabricating the semiconductor device in which parts of a gate electrode at the ends of a channel are lightly doped compared to the center part of the gate electrode, thereby eliminating a hump on a subthreshold current slope. To achieve the objects of the claimed invention, there is provided a semiconductor device that includes a semiconductor substrate divided into an isolation region and an active region. A gate oxide film is formed on a first upper surface of the active region. A gate electrode is formed on a second upper surface of the gate oxide film, the gate electrode having a first part and a second part. The first part is more lightly doped with impurities than the second part. A channel is formed in an upper end of the active region proximate the gate electrode.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls.

Abstract: A semiconductor device isolation structure includes a semiconductor substrate including an active region and a field region, an insulation layer buried in the active region of the substrate, and an isolation layer formed in the field region of the substrate deeper than the buried insulation layer. A method for isolating a semiconductor device includes the steps of preparing a semiconductor substrate, defining an active region and a field region in the substrate, forming an insulation layer buried in the active region of the substrate, and forming an isolation layer in the field region of the substrate to be deeper than the buried insulation layer. The invention applies to an SOI (Silicon On Insulator) provided with a SIMOX (Separation by Implanted Oxygen) type, for effectively overcoming interfacial defects between a buried oxide film and a semiconductor substrate, and improves a reliability of the semiconductor device by planarizing the same.

Abstract: A method of forming a shallow trench isolation on a substrate is disclosed. The method comprises: forming a pad oxide layer on the substrate; forming a dielectric layer on the pad oxide layer; forming at least one trench in the substrate; forming an oxide liner along the walls and bottom of the trench, the oxide liner formed from a UV/O3 process; and forming a CVD oxide layer for isolation atop the oxide liner and within the trench.

Abstract: A method for forming a field effect transistor (FET) is disclosed which includes forming an isolation region in a substrate of semiconductor material, anisotropically etching the substrate such that a sidewall spacer region of semiconductor material remains on a sidewall of the isolation region as a device region of the FET. The isolation region may then be recessed such that, after gate conductor deposition, the central channel region of the device region is enclosed by the gate conductor. A dopant concentration in at least one of the central portion of the device region or regions flanking the central portion are then altered to form source-drain regions having a first dopant type and a channel region having a second dopant type opposite the first dopant type.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: The semiconductor device and method of manufacturing the same according to the present invention has an object of reducing hem-pulling at a side wall of an isolation trench caused at an open space of a device isolation region having a well boundary at its bottom portion thereby to prevent structurally occurrence of punch-through. In an insulator filled device isolation method, an isolation trench for device isolation is formed by dry etching. If a second isolation trench intersects an intermediate portion of a first isolation like a T-shape, one side of the first isolation trench has an open space. In this case, the inclination angle of the side wall of the first isolation trench, opposed to the open space, is loosened and the side wall forms a shape whose hem is pulled out on the bottom portion. In this case if a well boundary exists along the lengthwise direction at the bottom of the first isolation trench, the structure tends to cause punch-through easily.

Abstract: A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking

Abstract: A semiconductor manufacturing process for producing MOS integrated circuits having two gate oxide thickness is provided. A first gate dielectric is formed on an upper surface of a semiconductor substrate. Thereafter, a masking layer is deposited on the first dielectric layer and patterned such that the first dielectric layer is exposed above a second region of the semiconductor substrate. The semiconductor wafer is then subjected to a thermal oxidation process such that a second gate dielectric is formed within the exposed second region of the semiconductor substrate. The second gate dielectric preferably has an oxide thickness that is unequal to the oxide thickness of the first gate dielectric layer. Thereafter, gate structures and source/drain structures are fabricated such that the integrated circuit includes a first transistor having a first gate dielectric thickness and a second transistor having a second gate dielectric thickness.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: An active silicon-on-insulator region isolation structure is provided that includes an active bulk substrate region (24), an active silicon-on-insulator region (22), and a transition region positioned between the active bulk substrate region (24) and the active silicon-on-insulator region (22). The active silicon-on-insulator region (22) includes a silicon-on-insulator film (16) positioned above a buried insulator layer (18). The transition region includes a sloping portion of the buried insulator layer (18) and a tapered edge portion of the silicon-on-insulator film (16).

Abstract: According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: In producing a CMOS circuit, an n-channel MOS transistor and a p-channel MOS transistor are formed in a semiconductor substrate. In situ p-doped, monocrystalline silicon structures are formed by epitaxial growth selectively with respect to insulating material and with respect to n-doped silicon, such silicon structures being suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. The source/drain regions of the n-channel MOS transistor are produced beforehand by means of implantation or diffusion. Owing to the selectivity of the epitaxy that is used, it is not necessary to cover the n-doped source/drain regions of the n-channel MOS transistor during the production of the p-channel MOS transistor.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.

Abstract: Isolation regions for a semiconductor layer of a semiconductor-on-insulator substrate are fabricated by forming a patterned implantation mask on the semiconductor layer. The patterned implantation mask includes mask sidewalls. An implantation masking film is formed on the sidewalls of the patterned implantation mask. Ions are implanted into the semiconductor layer, using the patterned implantation layer and the implantation masking film as a mask, to thereby form a doped region in the semiconductor layer. Sidewall spacers are formed on the implantation masking film, opposite the patterned implantation mask. The doped region between the sidewall spacers is etched to thereby define a trench in the semiconductor layer between the sidewall spacers and a doped edge layer in the semiconductor layer which extends from the trench to the implantation masking film. Insulating material is then formed in the trench.

Abstract: An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpendicular to the main surface of a semiconductor substrate in the sidewall oxide film has a peak at the interface between the semiconductor substrate and the sidewall oxide film. As a result, an interface state at the interface between the sidewall oxide film and the main surface of the semiconductor substrate is suppressed, resulting in decrease of the probability at which hot carriers are trapped in the interface state. Accordingly, the hot carrier resistance is improved.