Isolation By Pn Junction Only Patents (Class 438/220)
  • Patent number: 10546920
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Ralf Rudolf
  • Patent number: 10121704
    Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: November 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9905477
    Abstract: Inverters and methods of manufacture thereof are disclosed. In some embodiments, an inverter includes a substrate and a first tunnel FET (TFET) disposed over the substrate. The first TFET is a first fin field effect transistor (FinFET). A second TFET is over the first TFET. The second TFET is a second FinFET. A junction isolation region is disposed between a source of the first TFET and a source of the second TFET.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Yi Peng
  • Patent number: 9601625
    Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Fang Cheng, Yen-Lin Liu, Chen-Chih Wu, Chien-Yuan Lee
  • Patent number: 9281248
    Abstract: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Pushkar Ranade, Scott E. Thompson
  • Patent number: 9136325
    Abstract: A device structure is provided to reduce the leakage current of semiconductor devices with a floating buried layer (FBL), includes a substrate, a first epitaxial layer, a split floating buried layer, a second epitaxial layer, a doped trench, a protected device, a surface junction termination extension (S-JTE) and a scribe street. The device and the S-JTE are designed at the second epitaxial layer and the split floating buried layer at the joint of the first and second epitaxial layers. The doped trench is penetrated through the second epitaxial layer and connected to the split floating buried layer. The substrate, the first and second epitaxial layers feature the same typed doping which is opposite to that of split floating buried layer and doped trench.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 15, 2015
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Kai-Zhou Tan, Zhao-Huan Tang, Rong-Kan Liu, Yong Liu
  • Patent number: 9029235
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: May 12, 2015
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8981480
    Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Lim, Satoru Yamada, Sung-Duk Hong
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magriā€²
  • Patent number: 8828843
    Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 9, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Yaw-Wen Hu, Jung-Chang Hsieh, Kuen-Shin Huang, Jian-Wei Chen, Ming-Tai Chien
  • Patent number: 8786015
    Abstract: A super-junction semiconductor device includes a drift layer including an alternating-conductivity-type layer that includes n-type region and p-type region arranged alternately in parallel to the first major surface of an n-type substrate. These alternating regions extend deep in a direction perpendicular to the first major surface. The first major surface includes a main device region with a gate electrode and a main source electrode and sensing device region with a gate electrode and a sensing source electrode. There is a common drain electrode on the second major surface of the substrate. There is a separation region between the main device region and the sensing device region. It includes an n-type region and p-type regions in the n-type region. The p-type regions are in an electrically floating state in the directions parallel and perpendicular to the first alternating-conductivity-type layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 22, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takahiro Tamura, Yasuhiko Onishi
  • Patent number: 8772869
    Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Syotaro Ono
  • Patent number: 8729640
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 20, 2014
    Assignee: Silicon Space Technology Corporation
    Inventor: Wesley H. Morris
  • Patent number: 8598706
    Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Publication number: 20130059421
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 7, 2013
    Inventor: Wesley H. Morris
  • Patent number: 8377756
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: February 19, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Matocha, Peter Sandvik, Zachary Stum, Peter Losee, James McMahon
  • Patent number: 8263472
    Abstract: A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein
  • Patent number: 8236639
    Abstract: A semiconductor device manufacturing method is a method of forming a semiconductor device that includes a cell part that includes plural transistor cells in each of which a gate of a trench type is formed in a semiconductor layer, and diffused layers are formed on both sides of the gate, and a guard ring part that surrounds the cell part. The semiconductor device manufacturing method includes forming an interlayer dielectric film on a surface of the semiconductor layer in which the gate and the diffused layers are formed; reducing a thickness of the interlayer dielectric film formed in the cell part through etch back; forming a contact part having a shape of a hole or a groove in the interlayer dielectric film at a position above the diffused layer; and forming a metal film on the interlayer dialectic film.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: August 7, 2012
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Hiroaki Kikuchi, Katsunori Kondo, Shigeru Shinohara, Osamu Takahashi, Tomoaki Yamabayashi
  • Patent number: 8097502
    Abstract: Provided is a semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device. The semiconductor light emitting device includes a substrate, at least two light emitting cells located on the substrate and formed by stacking semiconductor material layers, a reflection layer and a transparent insulating layer sequentially stacked between the light emitting cells, and a transparent electrode covering the upper surface of the light emitting cells.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: January 17, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventor: Jeong-wook Lee
  • Patent number: 8053303
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: John E. Barth, Jr., Kerry Bernstein, Francis R. White
  • Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Publication number: 20110086478
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 14, 2011
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 7875512
    Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: forming a first region and a second region in a semiconductor substrate by forming an element isolation region; forming an insulating film on the semiconductor substrate in the first region and the second region; forming a first metal film on the insulating film in the first region and in the second region; removing the first metal film in the second region; forming a second metal film on the first metal film in the first region and on the insulating film in the second region; and flattening top surfaces in the first region and the second region by performing a flattening process.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akiko Nomachi
  • Patent number: 7858466
    Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: December 28, 2010
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
  • Patent number: 7855407
    Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 21, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hee Sung Shim
  • Patent number: 7687338
    Abstract: Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sameer Jain, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Jang H. Sim
  • Patent number: 7674683
    Abstract: A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: March 9, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kurt D. Beigel
  • Patent number: 7670893
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: March 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Glenn J Leedy
  • Patent number: 7608895
    Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: October 27, 2009
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chen
  • Publication number: 20090148988
    Abstract: Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 11, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameer Jain, Shreesh Narasimha, Karen A. Nummy, Viorel Ontalus, Jang H. Sim
  • Patent number: 7485523
    Abstract: The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in the substrate, wherein the second doped regions are located adjacent to both sides of the first doped region respectively, and the first doped region is separated from the second doped regions with an isolation region. A gate structure is formed on the substrate between the second doped regions and a source/drain region having the second doped region is formed in the substrate adjacent to both sides of the gate structure.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: February 3, 2009
    Assignee: United Microelectronics Corp.
    Inventor: Anchor Chen
  • Patent number: 7422938
    Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
    Type: Grant
    Filed: August 14, 2004
    Date of Patent: September 9, 2008
    Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) Limited
    Inventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
  • Patent number: 7407851
    Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: August 5, 2008
    Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
  • Publication number: 20080099846
    Abstract: A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.
    Type: Application
    Filed: May 2, 2007
    Publication date: May 1, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki Ohta
  • Publication number: 20080003738
    Abstract: In pattern-forming ferroelectric capacitor structures by a one mask etching, after an Ir film to be a lower electrode film is formed, an AlOx film to be an oxide reduction film reducing an Ir oxide which is formed on a surface layer of the lower electric film is deposited on the lower electrode film, and then this oxide reduction film is removed by, for example, a dilute hydrofluoric acid treatment.
    Type: Application
    Filed: October 27, 2006
    Publication date: January 3, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Katsuyoshi Matsuura
  • Patent number: 7052939
    Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 30, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wen Ling M. Huang, Sushil Bharatan, Carl Kyono, David J. Monk, Kun-Hin To, Pamela J. Welch
  • Patent number: 6989309
    Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. Particularly, a P-type dopant may diffuse farther up into an epitaxial layer than an N-type dopant to form an up-retro well.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: January 24, 2006
    Assignee: Linear Technology Corporation
    Inventor: Francois Hebert
  • Patent number: 6943072
    Abstract: An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isolation region transistors (320) are those areas with a conductor (130) over an isolation region (120) with no channel stop implant (140). This provides an isolation region transistor (320) with a lower threshold voltage than the areas with channel stop implant (140). The voltage threshold of the isolation region transistors 320 are adjustable to a range of voltages by varying the length of channel stop implant (140). The apparatus may be fabricated using conventional fabrication processes.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: September 13, 2005
    Assignee: Altera Corporation
    Inventor: Dominik J. Schmidt
  • Patent number: 6940137
    Abstract: The present invention provides a semiconductor device 200 having an angled compensation implant, a method of manufacture therefore and a method of manufacturing an integrated circuit including the angled compensation implant. In one embodiment, the method of manufacturing the semiconductor device 200 includes creating a halo implant 240 in a substrate 210, introducing a compensation implant 260 in the substrate 210 at an angle abnormal to the substrate 210 and forming a source/drain region 250 above the compensation implant 260, the angle reducing a capacitance associated with the halo implant 240 or the source/drain region 250. The method further includes placing a gate structure 230 over the substrate 210.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: September 6, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Jihong Chen, Zhiqiang Wu, Kaiping Liu
  • Patent number: 6887750
    Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages provided in a common substrate. The method includes: (a) introducing a first impurity of a second conductivity type by an ion implantation in a specified region of a semiconductor substrate of a first conductivity type; (b) forming an oxide film on a surface of the semiconductor substrate, and diffusing the first impurity by a heat treatment in an atmosphere that does not include oxygen to form a first well of the second conductivity type; and (c) introducing a second impurity of the first conductivity type through the oxide film in a specified region of the first well, and diffusing the second impurity by a heat treatment to form a second well of the first conductivity type.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: May 3, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Masahiro Hayashi
  • Patent number: 6878568
    Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: April 12, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Howard Rhodes, Chandra Mouli
  • Patent number: 6878595
    Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: April 12, 2005
    Assignee: Full Circle Research, Inc.
    Inventor: James P Spratt
  • Publication number: 20040241931
    Abstract: It is an object of the present invention to provide a display device that has a structure of an electrode where a residue of a transparent conductive film is not generated when a weak acid solution is used in etching, which is particularly appropriate for an electrode of a light-emitting element.
    Type: Application
    Filed: March 17, 2004
    Publication date: December 2, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Noriko Miyagi, Shingo Eguchi
  • Patent number: 6781206
    Abstract: Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P− substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-type region is formed at the surface of this N well. A pair of N++ type regions are formed at the surface of P-type region. A gate electrode is formed on a portion of P-type region interposed between N++ type regions. N++ type region is connected to ground while N++ type region is electrically connected to isolation region. Accordingly, current is restricted from flowing between the N-type island region for output and the passive N-type island region so as to obtain a semiconductor device in which occurrence of malfunctions is prevented.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Akio Uenishi
  • Patent number: 6780700
    Abstract: A method of forming a MOS or CMOS device on a silicon substrate, includes preparing a substrate to contain conductive regions having device active areas therein; forming a gate electrode on the active areas; depositing and forming a gate electrode sidewall insulator layer on each gate electrode; implanting ions of a first type to form a source region and a drain region in one active area and implanting ions of a second type to form a source region and a drain region in the other active area.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: August 24, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Katsuji Iguchi, Sheng Teng Hsu, Yoshi Ono, Jer-shen Maa
  • Patent number: 6589834
    Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: July 8, 2003
    Assignee: Alliance Semiconductor Corporation
    Inventors: Chitranjan N. Reddy, Ritu Shrivastava
  • Patent number: 6589835
    Abstract: A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 8, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6582997
    Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: June 24, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jian-Hsing Lee, Shui-Hun Chen, Jiaw-Ren Shih
  • Patent number: 6552256
    Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 22, 2003
    Assignee: The Regents of the University of California
    Inventors: Ali Shakouri, Christopher J. LaBounty, John E. Bowers