Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.

Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.

Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Abstract: A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.

Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: The closing plates (61b), (61c) are provided on the both end portions of the cylindrical insulator body (61a), the gas introduction tube for introducing a gaseous substance is inserted into one plate (61b) of the closing plates of the plasma chamber (61) for making the gaseous substance plasmatic within it, and on the other plate (61c), the plasma radiation outlet (61d) is provided. Then, nearby the plasma jet (63) outgoing from the radiation outlet, the electrode (64) for applying a high electric field of an ion trapper is provided so as to be opposed to the grounded electrode (65) interposed the plasma jet between them. This electrode for applying a high electric field is fixed on the grounded metal plate (61e) provided on the other plate (61c) via the insulation porcelain (66) made of MgO or quartz.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region is proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: The closing plates (61b), (61c) are provided on the both end portions of the cylindrical insulator body (61a), the gas introduction tube for introducing a gaseous substance is inserted into one plate (61b) of the closing plates of the plasma chamber (61) for making the gaseous substance plasmatic within it, and on the other plate (61c), the plasma radiation outlet (61d) is provided. Then, nearby the plasma jet (63) outgoing from the radiation outlet, the electrode (64) for applying a high electric field of an ion trapper is provided so as to be opposed to the grounded electrode (65) interposed the plasma jet between them. This electrode for applying a high electric field is fixed on the grounded metal plate (61e) provided on the other plate (61c) via the insulation porcelain (66) made of MgO or quartz.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: The cell density of power MOSFET used as a switch is determined by the width of the trench formed in the device, the processing limit of which is limited by the spatial resolution of the exposure apparatus used in the photolithographic process. This invention provides a method of manufacturing such devices which overcomes the processing limitation imposed by the exposure apparatus, and doubles the cell density and reduces the input capacitance for further reducing the on-state resistance and improving the switching speed. By forming a second CVD oxide film over a first oxide film defining the opening for forming a trench and subsequent anisotropic RIE etching of the second film, a side-wall film is added to the mask pattern, which promotes a further reduction of the width of the trench by more than one half.

Abstract: A plasma processing method includes evacuating a vacuum chamber while supplying a gas into the vacuum chamber, thereby controlling an interior of the vacuum chamber to a pressure, and supplying a high frequency power of a frequency of 50 MHz-3 GHz to an antenna which is set opposite to a substrate placed to a substrate electrode in the vacuum chamber and which has a structure with a dielectric member held between a wall face of the vacuum chamber opposite to the substrate and a metallic plate, thereby generating plasma inside the vacuum chamber and processing the substrate, wherein the high frequency power is supplied to satisfy a relation 3r<c/(f·&egr;½)<9r when c is a light velocity (m/sec), f is a frequency (Hz) of the high frequency power, &egr; is a relative permittivity of the dielectric member and, r is a half (m) of a longer line of a shape of the dielectric member.

Abstract: A method for detecting physical interference with desired transport of an article. The method includes the step of detecting an operative acoustic signal representing the structure-borne sound pattern of an article during said article transport, and detecting the presence of interference based on the acoustic signal. A system for performing the method includes a transport device adapted to transport the article through a predetermined path and an acoustic sensor in structure-borne acoustic contact with the transport device and capable of producing an acoustic signal indicative of physical interference.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses is performed by only one photoetching step, the process being capable of reducing the manufacturing cost, and speeding up the circuit operation by making the gate oxide film of the peripheral unit thinner than that of the I/O circuit unit. A resist mask having a given width ranging in a given range which will be formed on the silicon oxide film is formed in a gate forming area in a region where an embedded N-type layer will be formed in a P-type silicon substrate and it is desired to make the thickness of the gate oxide film thicker. The embedded N-type layer is also formed even immediately below the resist mask by conducting an ion implantation at a given energy via the resist mask.

Abstract: A method for processing a semiconductor device with improved latchup immunity and interwell isolation is described. Shallow trench isolation areas are formed on a semiconductor substrate to provide electrical isolation for active device N and P well areas. The active areas will contain complementary pairs of NMOS and PMOS deices. A trench is etched into the substrate at the boundary region between the active device regions. Before filling and capping the trench to form a complete STI structure, first one well region such as the N-well region is masked by photoresist to the center of the trench isolation structure, and an ion implant of acceptor atoms such as boron is implanted under the bottom surface of the open trench. The process is repeated for the P-well area except a donar source such as phosphorous or arsenic is used.

Abstract: A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls.

Abstract: A method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.

Abstract: A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is formed by implanting nitrogen and boron ions into the NMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the NMOS region at a selected concentration in the range of 1×1013 to 2×1015 ions per cm2 and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted in the NMOS region at a selected concentration in the range of 1×1012 to 1×1014 ions per cm2 and at a selected implantation energy in the range of 5-50 KeV. The shallow LDD regions in the PMOS region are formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and implantation energy levels.

Abstract: An implementation of sensor-driven run-to-run process control for semiconductor wafer fabrication integrates a robust, automated Fourier transform infrared reflectometer onto a wafer fabrication cluster tool. Cell controller software integrates an adaptive run-to-run controller, process tool recipe upload and download through a SECS port, sensor control, data archiving, and a graphical user interface.

Abstract: A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the field oxide layer within the scribe-line region to ensure the substrate and the conducting layer thereon are properly insulated. That prevents the leakage of the carriers generated by the Electro-optical effect to resolve the problem of an abnormally elevated output at the first pixel. In addition, a mask protects the dielectric layer on the scribe-line region from being etched, so the steep difference on the step height is improved to resolve the peeling of the photoresist. The field oxide layer under the dielectric layer covered by the dielectric layer then provides a better insulation.

Abstract: A method is provided for forming a triple well of a semiconductor memory device, where a second well of a second conductive type encloses a second well of a first conductive type. A single mask is used for ion implanting the base of the enclosing well and also the entire enclosed well, which inherently avoids misalignment. Additional doping is provided to the location where the sidewalls of the enclosing well join its base. This is accomplished either by a second, deeper ion implant of the sidewalls, or by ion implanting the base at an angle and rotating it, or both. Alternately, the single mask pattern is processed between the ion implantation steps to alter its width.

Abstract: A method for etching at least partially through a transition metal-containing layer disposed above a substrate is disclosed. The transition metal-containing layer is disposed below an etch mask. The method includes providing a plasma processing system having a plasma processing chamber, and configuring the plasma processing chamber to etch the transition metal-containing layer. The plasma processing chamber configuring process includes configuring the plasma processing chamber to receive a source gas that includes HCl and Ar, and configuring a power supply associated with the plasma processing chamber to supply energy to strike a plasma from the source gas. The plasma processing chamber configuring process further includes configuring the plasma processing chamber to etch at least partially the transition metal-containing layer with the plasma.

Abstract: A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of the substrate. A pad oxide film is grown on the substrate first surface covering the p-wells and/or n-wells. A diffusion barrier(s) is deposited on the substrate first surface and a substrate second surface to form an encapsulated structure. The encapsulated structure is annealed to activate the n-type and/or p-type areas. A mask material is applied over the diffusion barrier on the substrate first surface to define active device areas and a dry etch process is used to etch away the unmasked portions of the diffusion barrier. The mask material is stripped and a field oxide is grown on the substrate first surface. A portion of the field oxide and all of the diffusion barrier is removed, resulting in active areas surrounded by a field isolation structure.

Abstract: A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

Abstract: A method for fabricating a CMOS device having BILLI (buried implanted layers for lateral isolation) structure capable of effectively preventing latch-up is disclosed, having the following steps. A mask pattern is formed on the semiconductor substrate of a predetermined conductivity type to expose a region where the MOS transistor, having a same conductivity type as that of the substrate, is to be formed wherein the mask pattern has a vertical boundary face having a gradual slope. A buried layer is then formed in the form of island by ion-implanting the impurity ions into the substrate to pass through the mask pattern, the buried layer having a same conductivity type as that of the substrate, and being formed to be continuous under the vertical boundary face of the mask pattern.

Abstract: The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor substrate having therein a P-well and an N-well. Each of the N-well and P-well has therein a trench. The ions of the P-type dopant are implanted beneath each of the trenches in the P-well and the N-well to create a first P-type dopant concentration profile in the semiconductor substrate, wherein the P-well and the N-well are substantially unimplanted by the ions of the P-type dopant in active areas adjacent to the respective trenches therein. A second implanting ions of a P-type dopant is made into the semiconductor substrate. The second implanting is beneath each of the trenches in the P-well and the N-well to form a second P-type dopant concentration profile.

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate.

Abstract: A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it.

Abstract: An improved twin well formation method for a semiconductor device capable of improving the latch-up characteristic in DRAM device which requires a high integration density and of improving a recess problem which occurs due to the capacitor, which includes the steps of a first step which forms an insulation film on a semiconductor substrate having a first region and a second region; a second step which forms a first temporary film on an insulation film of the first region; a third step which forms a first side wall spacer at the first temporary side wall; a fourth step which implants a first conductive ion to a substrate of a second region; a fifth step which forms a second temporary film on a substrate of the second region; a sixth step which removes the first temporary film; a seventh step which implants a second conductive ion to a substrate of the first region; and an eighth step which anneals and removes the second temporary film and the first insulation spacer.

Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.