With Epitaxial Semiconductor Layer Formation Patents (Class 438/222)
  • Patent number: 10570517
    Abstract: Embodiments of the present invention provide apparatus and methods for performing UV treatment and chemical treatment and/or deposition in the same chamber. One embodiment of the present invention provides a processing chamber including a UV transparent gas distribution showerhead disposed above a substrate support located in an inner volume of the processing chamber, a UV transparent window disposed above the UV transparent gas distribution showerhead, and a UV unit disposed outside the inner volume. The UV unit is configured to direct UV lights towards the substrate support through the UV transparent window and the UV transparent gas distribution showerhead.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Amit Bansal, Dale R. Du Bois, Juan Carlos Rocha-Alvarez, Sanjeev Baluja, Scott A. Hendrickson, Thomas Nowak
  • Patent number: 10516040
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, where a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer with a first growth rate around a sidewall adjacent to the gate structures that is greater than a second growth rate at a central portion; and, in the chamber, partially removing the epitaxial silicon-rich layer with an etchant with a first etching rate around the sidewall adjacent to the gate structures that is greater than a second etching rate at the central portion.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Po-Jung Chiang, Yen-Hsiu Chen, Yeur-Luen Tu
  • Patent number: 10497783
    Abstract: The invention provides a semiconductor structure and a method of preparing a semiconductor structure, which solves the problems of easy cracking, large warpage and large dislocation density which exist in a semiconductor compound epitaxial structure epitaxially grown on a substrate in the prior art. The semiconductor structure includes: a substrate; at least one periodic structure disposed over the substrate; wherein each of the periodic structures includes at least one period, each period including a first periodic layer and a second periodic layer which are sequentially stacked in an epitaxial direction.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 3, 2019
    Assignee: ENKRIS SEMICONDUCTOR, INC
    Inventors: Peng Xiang, Kai Cheng
  • Patent number: 10496630
    Abstract: Performing a distributed database transaction using parallel writes to a distributed append-only database system is provided. A central database and a plurality of distributed databases, also known as “shards”, may be used. A request made to implement a distributed transaction, requiring updates to one or more shards, results in a monotonically increasing identification (ID) number being assigned to a change set. The request and change set may be registered at the central database. Once the change set is completely written to all of the appropriate shards, the change set is marked as completed in the central database. After write completion, a change set ID boundary at the central database is advanced to indicate the current fully changed status of the distributed database.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: December 3, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jeffrey Darren Couckuyt, Joseph Schwartz, Sergey Y. Galuzo
  • Patent number: 10205452
    Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hikaru Tamura
  • Patent number: 10140780
    Abstract: Embodiments implement event- and/or condition-based machine monitoring for quality inspection in a manufacturing process. An application receives from a machine, an input comprising event(s) and/or condition(s) potentially affecting product quality. Such an event could be scheduled/unscheduled maintenance of the machine. An exemplary condition could be deviation an operating parameter of the machine that is being monitored. Based upon this input, the engine references a ruleset to output a level of Quality Assurance (QA) product inspection with a changed component (for example, including a more stringent tolerance requirement, an additional inspection step, and/or inspection of larger/additional product lots). Embodiments thus automatically link a rigor of product inspection with changes in machine state having the potential to degrade product quality.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: November 27, 2018
    Assignee: SAP SE
    Inventor: Christian Schelhaas
  • Patent number: 10068774
    Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1?xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1?yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1?zGez is formed on the second epitaxial layer. Z is smaller than y.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Min Huang, Hsiu-Ting Chen, Shih-Chieh Chang
  • Patent number: 10014256
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Yan A. Borodovsky, Mark C. Phillips
  • Patent number: 9911613
    Abstract: A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 6, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Hui-Mei Shih
  • Patent number: 9876070
    Abstract: A semiconductor device (100) comprises: a semiconductor substrate (1); a drift region (2) of a first conductivity type having a trench in part of an upper portion thereof and arranged on a first main surface of the semiconductor substrate (100); an electric field reducing region (4) of a second conductivity type arranged, in a bottom portion of the trench, only around a corner portion and not in a center portion; an anode electrode (9) embedded in the trench; and a cathode electrode (10) arranged on a second main surface of the semiconductor substrate (100) which is opposite to the first main surface.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: January 23, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Toshiharu Marui, Tetsuya Hayashi, Shigeharu Yamagami, Wei Ni, Kenta Emori
  • Patent number: 9865480
    Abstract: The present invention relates to an under-fill dam with high detection probability that is composed of a dry film solder resist and provided in the form of a fence around a chip device in order to prevent leaks of an under-fill material filled in a gap between a substrate and the chip device.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 9, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Byung-Ju Choi, Woo-Jae Jeong, Bo-Yun Choi, Kwang-Joo Lee, Min-Su Jeong
  • Patent number: 9679749
    Abstract: A grid assembly for a substrate processing system includes a first portion including a first body defining a central opening, an inlet, an outlet, and an upper manifold that is located in the first body and that is in fluid communication with the inlet or the outlet. A second portion is arranged adjacent to the first portion and includes a second body defining a central opening. A plurality of tubes is arranged in the central opening of the second body. First ones of the plurality of tubes are in fluid communication with the upper manifold. A lower manifold is located in the second body and is in fluid communication with the other one of the inlet or the outlet. Second ones of the plurality of tubes are in fluid communication with the lower manifold. The grid assembly is arranged between a remote plasma source and a substrate.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 13, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ivelin Angelov, Serge Kosche
  • Patent number: 9643149
    Abstract: The present invention relates to a method for the production of cross-linked carbon nanotube network which are selected from aerogels and xerogels with improved performance and characteristics thereof. The invention is also concerned with carbon nanotube networks which are selected from aerogels and xerogels produced by such processes and uses thereof.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 9, 2017
    Assignees: The Bio Nano Centre Limited, King Abdulaziz University
    Inventors: Milo Shaffer, Garcia Gallastegui Ainara, Abdullah Asiri, Shaeel Althabaiti
  • Patent number: 9589845
    Abstract: A method is provided for forming a fin cut that enables a single diffusion break in very dense CMOS structures formed using bulk semiconductor substrates. A dummy gate is removed from a finned structure to expose the top regions of the fins, the bottom fin regions being within a shallow trench isolation region. Selective vapor phase etching follows sequential ion implantation of the top and bottom fin regions to form a diffusion break cut region. The non-implanted regions of the substrate and the shallow trench isolation region remain substantially intact during each etching procedure. Double diffusion break cut regions are also enabled by the method.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Vamsi K. Paruchuri, Alexander Reznicek
  • Patent number: 9514993
    Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: December 6, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Wei Yu, Ted Ming-Lang Guo, Hsu Ting, Yu-Ren Wang
  • Patent number: 9472465
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Bongki Lee, Jin Ping Liu, Bharat Krishnan
  • Patent number: 9397585
    Abstract: Techniques are disclosed for systems and methods to provide shock impact mitigation for MEMS structures. A MEMS structure may include one or more actuators. An actuator may include a first frame having a spine, where the spine includes a body and a tip. The actuator may include a second frame connected to the first frame and including a shock stop, where the shock stop includes a surface in proximity to the spine tip. An actuator may include a shock cushion spring fixed relative to the spine tip and situated substantially between the spine tip and the shock stop surface, where the shock cushion spring is adapted to protect the spine tip from contact with the shock stop surface.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 19, 2016
    Assignee: DIGITALOPTICS CORPORATION MEMS
    Inventors: Xiaolei Liu, Xiaojun Huang, Robert J. Calvet
  • Patent number: 9396676
    Abstract: To provide a semiconductor device which operates stably with few malfunctions due to noise, with low power consumption, and little variation in characteristics; a display device including the semiconductor device; and an electronic device including the display device. An output terminal is connected to a power supply line, thereby reducing variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, change in characteristics of the transistor is reduced by a signal line for reverse bias.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasunori Yoshida
  • Patent number: 9370854
    Abstract: The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Hsin Kuo, Fu-Ming Huang
  • Patent number: 9308479
    Abstract: The present invention relates to a method for the production of cross-linked carbon nanotube networks which are selected from aerogels and xerogels with improved performance and characteristics thereof. The invention is also concerned with carbon nanotube networks which are selected from aerogels and xerogels produced by such processes and uses thereof.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 12, 2016
    Assignees: The Bio Nano Centre Limited, King Abdulaziz University
    Inventors: Milo Shaffer, Ainara Garcia Gallastegui, Abdullah Asiri, Shaeel Althabaiti
  • Patent number: 9164059
    Abstract: The present invention relates to ion mobility spectrometry, in particular to methods and devices for generating and delivering of ammonia gas as dopant into the ionization region of an ion mobility spectrometer. It provides an ion mobility spectrometer (IMS) with an ion source and device for generating ammonia gas, wherein the device comprises a dopant reservoir filled with alkali metal nitride or alkaline earth metal nitride, preferably lithium nitride and/or magnesium nitride, said reservoir being fluidly coupled to the ion source and to a water reservoir.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: October 20, 2015
    Inventor: Michael Blaschke
  • Patent number: 9064745
    Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Kangguo Cheng, Joseph Ervin, Juntao Li, Ravi M. Todi, Geng Wang
  • Patent number: 9034706
    Abstract: A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Tzu-Wei Kao, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9012310
    Abstract: Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai
  • Patent number: 9006057
    Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Changliang Qin, Peizhen Hong, Huaxiang Yin
  • Publication number: 20150084108
    Abstract: A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors.
    Type: Application
    Filed: March 28, 2014
    Publication date: March 26, 2015
    Inventor: Samar Saha
  • Patent number: 8962418
    Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Hoshino
  • Patent number: 8951858
    Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 8940595
    Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
  • Publication number: 20150024561
    Abstract: Systems and methods of fabricating a FinFET in large scale integrated circuit are disclosed. One illustrative method relates to a dummy gate process, wherein the fin structure is only formed in the gate electrode region by performing a photolithography process and an etching of a first dummy gate on a flat STI surface using chemical mechanical polishing, forming drain and source regions, depositing a medium dielectric layer, polishing the medium dielectric layer till the top of the first dummy gate is exposed through the chemical mechanical polishing process again, removing the dummy gate material via a dry etching and a wet etching, and continuously etching the STI dielectric layer with the hard mask formed by the medium dielectric layer, thereafter performing the deposition of real gate dielectric and gate electrode material to complete the device structure.
    Type: Application
    Filed: May 2, 2012
    Publication date: January 22, 2015
    Inventors: Ming Li, Ru Huang
  • Patent number: 8937366
    Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 20, 2015
    Assignee: STC.UNM
    Inventors: Sang M. Han, Darin Leonhardt, Swapnadip Ghosh
  • Patent number: 8936995
    Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Marcus Culmsee, Chris Stapelmann, Bee Kim Hong, Roland Hampp
  • Patent number: 8927386
    Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 6, 2015
    Assignees: CSMC Technologies FAB1 Co., Ltd., CSMC Technologies FAB2 Co., Ltd.
    Inventors: Tzong Shiann Wu, Genyi Wang, Leibing Yuan, Pengpeng Wu
  • Patent number: 8927363
    Abstract: A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8916445
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8912068
    Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Ho Lee, Seung-Joon Jeon, Tae-Hang Ahn
  • Patent number: 8895383
    Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8859320
    Abstract: Disclosed in a method that is for producing a solar cell and that is characterized by performing an annealing step on a semiconductor substrate before an electrode-forming step. By means of performing annealing in the above manner, it is possible to improve the electrical characteristics of the solar cell without negatively impacting reliability or outward appearance. As a result, the method can be widely used in methods for producing solar cells having high reliability and electrical characteristics.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Ryo Mitta, Mitsuhito Takahashi, Hiroshi Hashigami, Takashi Murakami, Shintarou Tsukigata, Takenori Watabe, Hiroyuki Otsuka
  • Patent number: 8841177
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8841181
    Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
  • Patent number: 8828781
    Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 9, 2014
    Assignees: Tower Semiconductor Ltd., Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Patent number: 8815698
    Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8809151
    Abstract: In sophisticated transistors, a specifically designed semiconductor material, such as a strain-inducing semiconductor material, may be sequentially provided in the drain region and the source region, thereby enabling a significant degree of lateral extension of the grown semiconductor materials without jeopardizing mechanical integrity of the transistor during the processing thereof. For example, semiconductor devices having different drain and source sides may be provided on the basis of sequentially provided embedded semiconductor materials.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Stephan-Detlef Kronholz, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8778758
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of electrode structures above a substrate. The method includes forming an insulating film on the plurality of electrode structures to make a gap between mutually-adjacent electrode structures. The method includes forming a silicon nitride film having compressive stress above the insulating film. The method includes forming a planarization film above the silicon nitride film. The method includes planarizing a surface of the planarization film by polishing by CMP (chemical mechanical polishing) method.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Kubota
  • Patent number: 8779525
    Abstract: A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 15, 2014
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc
    Inventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
  • Patent number: 8778753
    Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
  • Patent number: 8765545
    Abstract: A method of manufacturing a semiconductor device is disclosed. The exemplary method includes providing a substrate having a source region and a drain region. The method further includes forming a first recess in the substrate within the source region and a second recess in the substrate within the drain region. The first recess has a first plurality of surfaces and the second recess has a second plurality of surfaces. The method also includes epi-growing a semiconductor material in the first and second recesses and, thereafter, forming shallow isolation (STI) features in the substrate.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mei-Hsuan Lin, Chih-Kang Chao, Chih-Hsun Lin, Ling-Sung Wang