Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.

Abstract: A method for forming a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

Abstract: Embodiments provide a memory structure and its formation method. In those embodiments, a semiconductor substrate is provided. Discrete active areas arranged in rows and columns can be formed on the substrate. A first groove between two adjacent discrete active areas can be formed. The first groove can be filled with an insulating layer. Two second grooves along a row direction in each of the discrete active areas can be formed to divide the areas into a drain and two sources located on both sides of the drain. A third groove can be formed in part of the insulating layer on both sides of a bottom of the second groove. The third groove can expose a part of a surface of the sidewalls on both sides of the active area at the bottom of the second groove. The memory structure in those embodiment can help reduce current leakage.

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.

Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit.

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

Abstract: An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a junction, such as a Schottky junction, with the drift region, and a p-type junction barrier region on the silicon carbide layer. The p-type junction barrier region includes a p-type polysilicon region forming a P-N heterojunction with the drift region, and the p-type junction barrier region is electrically connected to the contact. Related methods are also disclosed.

Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

Abstract: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.

Abstract: A high voltage device includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on the substrate and between the source and the drain; and a second isolation structure. The second isolation structure includes a first isolation region and a second isolation region. The first isolation region is on the substrate and between the source and the drain, and is partially or totally covered by the gate. The second isolation region is in the substrate and below the gate, and has a depth in the substrate which is deeper than the depth of the first isolation region in the substrate, and the length of the second isolation region in a direction along an imaginary line connecting the source and the drain does not exceed one-third length of the first isolation region.

Abstract: A metal gate structure includes a substrate including a dense region and an iso region. A first metal gate structure is disposed within the dense region, and a second metal gate structure is disposed within the iso region. The first metal gate structure includes a first trench disposed within the dense region, and a first metal layer disposed within the first trench. The second metal gate structure includes a second trench disposed within the iso region, and a second metal layer disposed within the second trench. The height of the second metal layer is greater than the height of the first metal layer.

Abstract: Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases.

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract: A solid-state imaging sensor which has a first face and a second face, and includes an image sensing region and an electrode region, comprising a first portion including an insulating member and a wiring pattern, a second portion including a plurality of photoelectric conversion portions in the image sensing region, and a third portion including a plurality of microlenses in the image sensing region, wherein an opening is formed on the side of the first face in the electrode region so as to expose the wiring pattern, and the sensor includes a first film covering the plurality of microlenses, and a second film covering a side face of the opening and exposing part of the wiring pattern in the electrode region, with covering the first film in the image sensing region.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

Abstract: A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.

Abstract: A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract: Among other things, a semiconductor device comprising an aligned gate and a method for forming the semiconductor device are provided. The semiconductor device comprises a gate formed according to a multi-gate structure, such as a gate-all-around structure. A first gate portion of the gate is formed above a first channel of the semiconductor device. A second gate portion of the gate is formed below the first channel, and is aligned with the first gate portion. In an example of forming the gate, a cavity is etched within a semiconductor layer formed above a substrate. A dielectric layer is formed around at least some of the cavity to define a region of the cavity within which the second gate portion is to be formed in a self-aligned manner with the first gate portion. In this way, the semiconductor device comprises a first gate portion aligned with a second gate portion.

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract: A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3N4) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k?5, k?7.5, and k?20.

Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.

Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract: Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. Compared with conventional approaches to form contacts, the present disclosure reduces contact resistance and avoids a short circuit between a gate and contact plugs, while simplifying manufacturing process, increasing integration density, and lowering manufacture cost. According to the manufacturing method of the present disclosure, second shallow trench isolations are formed with an upper surface higher than an upper surface of the source/drain regions. Regions defined by sidewall spacers of the gate, sidewall spacers of the second shallow trench isolations, and the upper surface of the source/drain regions are formed as contact holes. The contacts are formed by filling the contact holes with a conductive material. The method omits the steps of etching for providing the contact holes, which lowers manufacture cost.

Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

Abstract: A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.

Abstract: A method for fabricating a semiconductor device with mini-SONOS cell is disclosed. The method includes: providing a semiconductor substrate having a first MOS region and a second MOS region; forming a first trench in the semiconductor substrate between the first MOS region and the second MOS region; depositing a oxide liner and a nitride liner in the first trench; forming a STI in the first trench; removing a portion of the nitride liner for forming a second trench between the first MOS region of the semiconductor substrate and the STI and a third trench between the STI and the second MOS region of the semiconductor substrate; and forming a first conductive type nitride layer in the second trench.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

Abstract: A method of making a semiconductor device includes forming a sacrificial layer above a semiconductor layer. Portions of the sacrificial layer are selectively removed to define a first set of spaced apart sacrificial fins over a first region of the semiconductor layer, and a second set of spaced apart sacrificial fins over a second region of the semiconductor layer. An isolation trench is formed in the semiconductor layer between the first and second regions. The isolation trench and spaces are filled with a dielectric material. The first and second sets of sacrificial fins are removed to define respective first and second sets of fin openings. The first set of fin openings is filled to define a first set of semiconductor fins for a first conductivity-type transistor, and the second set of fin openings is filled to define a second set of semiconductor fins for a second conductivity-type transistor.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.