Abstract: Provided are a plasma processing apparatus and a plasma processing method capable of improving uniformity of plasma processing without increasing a necessary output of a power supply. A plasma processing apparatus includes: a processing chamber performing processing using a plasma; and three or more electromagnetic wave introducing parts connected to the processing chamber to introduce into the processing chamber an electromagnetic wave for driving a reaction gas supplied into the processing chamber into a plasma state, wherein of combinations of every two adjacent ones of said three or more electromagnetic wave introducing means located in a region adjacent to said processing chamber, a distance between the two adjacent electromagnetic wave introducing means forming one of said combinations is different from a distance between the two adjacent electromagnetic wave introducing means forming another one of said combinations.

Abstract: [Object] To The invention provides an electro-optical device and a manufacturing method therefor which makes it possible to manufacture power source wiring lines more simply. [Solving Means] Power source wiring lines are formed by an inkjet method.

Abstract: A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.

Abstract: A semiconductor device comprises a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11,25). The gate dielectric (11,25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).

Abstract: A method for manufacturing a smart label web comprises smart labels placed one after and/or next to each other and comprising a circuitry pattern and an intergrated circuit on a chip therein. In the method, an electric contact is formed between the integrated circuit on the chip and the circuitry pattern on the smart label of the smart label web. The integrated circuit on the chip is attached to the circuitry of the smart label by means of a thermoplastic film on the surface of the chip.

Abstract: A memory cell of a SRAM comprises two drive MISFET and two vertical MISFETs. The p channel vertical MISFET are formed above the n channel drive MISFET. The vertical MISFETs respectively mainly comprise a square pole laminate comprising a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film comprising silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

Abstract: Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

Abstract: A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.

Abstract: A method for providing a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.

Abstract: A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.

Abstract: The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS·FETs.

Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: A metal gate complementary metal oxide semiconductor (CMOS) and a method of manufacturing the same is disclosed. The method includes depositing the metal gate electrode material as a final step before metallization of the device. Accordingly, the metal gate material is not subject to contamination during the fabrication process. The device is fabricated without the use of oxide spacers so that the finished device does not suffer from silicon faceting at the active silicon-to-shallow-trench-isolation-interface. Moreover, the dummy gate material is used to define planarization stops that allow precise planarization of the device during fabrication.

Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer. Thus, a high breakdown voltage semiconductor device and a manufacturing process therefor is provided, which includes a low breakdown voltage element region and a high breakdown voltage element region, and a high breakdown isolation region separates a high breakdown voltage region without impairing the characteristics of an element formed on the low breakdown voltage element region.

Abstract: A method of manufacturing a semiconductor component includes providing a substrate (110) having a first doping concentration and growing an epitaxial layer (120, 520) over the substrate. The epitaxial layer has a second doping concentration lower than the first doping concentration, and the epitaxial layer has at least two effective, as-grown thicknesses. The resulting composite substrate is suitable for an integrated circuit having both high and low voltage portions.

Abstract: A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.

Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.

Abstract: A manufacturing apparatus of a semiconductor device includes an introducing section, a process section, and a withdrawing section. The introducing section introduces a transfer box therein. The process section takes in the semiconductor substrate put in the introducing section and applies a prescribed processing to the semiconductor substrate. Further, the withdrawing section is arranged on a surface differing from the surface on which the introducing section is arranged and discharges the transfer box holding the semiconductor substrate withdrawn from the process section of the semiconductor substrate.

Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

Abstract: A process of manufacturing a semiconductor device having a dual gate CMOS transistor in which an nMOS transistor in the dual gate CMOS transistor is formed by the steps of: (a) forming a gate insulating film and a silicon film on a semiconductor substrate; (b) implanting n-type impurities into the silicon film in an nMOS region of the semiconductor substrate; (c) forming a conductive film on the silicon film; and (d) patterning the silicon film and the conductive film into a gate electrode.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

Abstract: A field effect transistor on an SOI wafer has a non-floating body which is tied to the substrate of the wafer by a bridge of conductive material such as semiconductor material. The bridge is created by selectively etching through a portion of a surface semiconductor layer and the underlying portion of a buried insulator layer, thereby making an opening or trench which exposing some of the semiconductor substrate of the SOI wafer. Then the opening is filled, for example by growth of a replacement semiconductor material by selective epitaxy.

Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.

Abstract: A method of manufacturing a transistor. The method comprising the steps of providing a substrate. The substrate comprises a gate oxide layer formed thereon, a polysilicon layer formed on the gate oxide layer, an offset spacer formed on a sidewall of the polysilicon layer and the gate oxide layer and a source/drain formed in the substrate. A conformal dielectric layer is formed over the polysilicon layer, the offset spacer and the source/drain. A spacer is formed on the sidewall of a portion of the conformal dielectric layer over the offset spacer. A portion of the conformal dielectric layer is removed to expose the polysilicon layer and the source/drain. A selective epitaxial growth process is performed to form an epitaxial layer on the polysilicon layer and the source/drain. A portion of the epitaxial layer on the polysilicon layer, the polysilicon layer and the gate oxide layer together form a T-type gate structure.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.

Abstract: According to a method for manufacturing a semiconductor device having a junction boundary where SiGe of a first conductivity type and Si or SiGe of a second conductivity type come in contact with each other, a portion where the junction boundary is exposed on the surface is cleaned with a first solution containing hydrofluoric acid and is then cleaned with a second solution containing sulfuric acid.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Abstract: A method of forming a submerged semiconductor structure is provided. According to one embodiment, a recessed area is formed on the surface of a wafer of first conductivity type. A dielectric layer is then formed on the surface of the wafer and recessed area. Polysilicon may then deposited in the recessed area to form a polysilicon region, and a dopant of second conductivity type may be selectively implanted in a first defined region. An epitaxial layer may then be grown over the structure. In one embodiment, the first defined region may pattern the implantation of the dopant to form a submerged transistor. In another embodiment, a second region under the recessed area is also implanted with a dopant of second conductivity type, and the first defined region may control the selective implantation to form a submerged capacitor.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

Abstract: A light emitting diode (LED) is disclosed. An emitted light can be prevented from being absorbed by a substrate by using a bragg reflector layer with high reflectivity. The present invention provides a bragg reflector layer comprising a plurality of high aluminum-contained AlGaAs/AlGaInP layers or high aluminumcontained AlGaAs/low aluminum-contained AlGaInP layers formed on the substrate before the epitaxial structure of the light emitting diode being formed. Since the high aluminum-contained AlGaAs is oxidized and formed an oxide of a lower refraction index, the reflectivity and high reflection zones of the oxidized bragg reflector layer are much larger. According to the electrical insulation characteristic of the oxide, the bragg reflector layer can limit the current within the oxidized regions of high aluminum-contained AlGaAs layer. Therefore, the aforementioned light emitting diode structure has a higher brightness than the conventional light emitting diode.

Abstract: A method of fabricating a CMOS transistor to construct shallow drain extenders (30) using a replacement gate design. The method involves forming epitaxial layers (30) and (220) the will later function as shallow drain extensions. The etching of the replacement gate (220) and the formation of inner sidewalls (90) serve to define the transistor gate length.

Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

Abstract: An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at least partly surrounded by the monocrystalline region. An epitaxial layer is grown on the monocrystalline region. The electrically insulating region is at least partly overgrown laterally with the epitaxial layer, thereby forming an epitaxial closing joint above the electrically insulating region due to the overgrowth. The epitaxial layer is at least partly removed above the electrically insulating region, thereby the epitaxial closing joint is at least partly removed.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.

Abstract: In a semiconductor device, adjacent ones of aluminum wirings are electrically isolated from each other through an interlayer insulation film containing a void space portion which is disposed between the adjacent ones of the aluminum wirings in a condition in which the void space portion makes its lower surface substantially flush with a lower surface of each of the aluminum wirings. A trench is formed between the adjacent ones of the aluminum wirings in an upper surface of a semiconductor substrate. Each of the trench and the aluminum wirings has its side surfaces covered with a damage preventing silicon oxide film, i.e., side-wall insulation film which is used to form the trench. The trench is filled with the interlayer insulation film.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: A semiconductor integrated circuit comprises a substrate (1) of a first conduction type semiconductor material, an epitaxial layer (10) which is carried by the substrate (1) and which is of a second conduction type semiconductor material different to the first conduction type material, a well (3) of semiconductor material in the epitaxial layer and a semiconductor material, the epitaxial layer (10) being substantially depleted of charges is a region substantially beneath the well (3).

Abstract: Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the conductive layer patterns, the semiconductor device including: conductive layer patterns formed on a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and the conductive layer patterns; well regions formed in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and gate and source/drain electrodes formed on the well regions, and a method for fabricating the semiconductor device including the steps of: forming conductive layer patterns on a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate including the conductive layer patterns; forming well regions in the semiconductor layer and the semiconductor subs

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate.

Abstract: Nonvolatile memory and method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size, the nonvolatile memory including a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a line form of a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gate in a direction the same with the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region, a cont

Abstract: A method is disclosed for forming an epitaxial layer of a semiconductor material over a metal structure disposed upon a surface of a semiconductor substrate, the metal being characterized by a negative Gibbs free energy for the formation of a compound of the metal and the semiconductor material. The method comprises the steps of: a) placing the substrate in a reactor vessel having a base pressure in the ultra high vacuum range, b) bringing the substrate to an elevated temperature, and c) flowing, over said substrate, a halogen-free precursor gas of molecules comprising the semiconductor material. Typically, the metal structure characterized by feature dimensions of less than 2.0 microns. Preferably, the metal is tungsten, the semiconductor material is silicon and the gas comprises a silane of the form SinH(2n+2), where n is a positive integer.