Including Device Responsive To Nonelectrical Signal Patents (Class 438/24)
  • Patent number: 11114628
    Abstract: A method of manufacturing flexible OLED display panel is provided. The method comprises following steps. Providing a glass carrier, sequentially forming a flexible substrate, a low temperature poly-Si layer and OLED element layer on a surface of the glass carrier; forming a planar layer on a second surface of the glass carrier which is away from the flexible substrate and obtaining a planning OLED display panel; removing the glass carrier by laser lift-off the planning OLED display panel and obtaining the flexible OLED display panel. The method could reduce the problem of lower peeling successful rate caused by the unevenly distributing in the flexible substrate during the laser lift-off process.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 7, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiang Jin
  • Patent number: 10861998
    Abstract: Disclosed is a method of manufacturing a compound semiconductor solar cell including forming a compound semiconductor layer; and forming a defect-removed portion formed of an empty space through removing a portion of the compound semiconductor layer where a defect existed prior to removal. The forming of the defect-removed portion includes forming a mask material layer on the compound semiconductor layer; forming a mask layer through forming an opening at a portion of the mask material layer corresponding to the portion of the compound semiconductor layer where the defect exists; and etching the compound semiconductor layer for removing the portion of the compound semiconductor layer where the defect exists through the opening of the mask layer to form the defect-removed portion.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 8, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Junoh Shin, Kitae An, Huijae Lee, Hyeunseok Cheun
  • Patent number: 10762836
    Abstract: An electronic display row drivers or column drivers that send reference currents or voltages to microdrivers to be used to drive micropixels to particular levels. The microdrivers, in turn, ship current to micropixels that display images based at least in part on the shipped current.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 1, 2020
    Assignee: Apple Inc.
    Inventors: Hopil Bae, Wei H. Yao, Mohammad B. Vahid Far, Yafei Bi, Xiaofeng Wang, Thomas Charisoulis, Hasan Akyol, Henry C. Jen, Derek K. Shaeffer
  • Patent number: 10629576
    Abstract: An optical proximity sensor arrangement comprises a semiconductor substrate (100) with a main surface (101). A first integrated circuit (200) comprises at least one light sensitive component (201). The first integrated circuit is arranged on the substrate at or near the main surface. A second integrated circuit (300) comprises at least one light emitting component (301), and is arranged on the substrate at or near the main surface. A light barrier (400) is arranged between the first and second integrated circuits. The light barrier being designed to block light to be emitted by the at least one light emitting component from directly reaching the at least one light sensitive component. A multilayer mask (500) is arranged on or near the first integrated circuit and comprising a stack (501) of a first layer (502) of first elongated light blocking slats (503) and at least one second layer (504) of second elongated light blocking slats (505).
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 21, 2020
    Assignee: ams AG
    Inventors: David Mehrl, Greg Stoltz
  • Patent number: 10615309
    Abstract: A method for producing a light-emitting diode with a stacked structure, having a first region and a second region and a third region, wherein all three regions have a substrate and an n-doped lower cladding layer and an active layer generating electromagnetic radiation, wherein the active layer includes a quantum well structure, and a p-doped upper cladding layer, and the first region additionally has a tunnel diode formed on the upper cladding layer and composed of a p+ layer and an n+ layer, and an n-doped current distribution layer. The current distribution layer and the n-doped contact layer are covered with a conductive trace. At least the lower cladding layer, the active layer, the upper cladding layer, the tunnel diode, and the current distribution layer are monolithic in design. The second region has a contact hole with a bottom region.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 7, 2020
    Assignee: Azur Space Solar Power GmbH
    Inventors: Thomas Lauermann, Wolfgang Koestler, Bianca Fuhrmann
  • Patent number: 9916726
    Abstract: A gaming system includes a credit mechanism configured to receive credit input by a player for contribution to a credit balance and a display configured to display a plurality of standard symbol positions and optionally one or more additional symbol positions. The system also includes a betting module configured to determine a bet amount and game play instructions on commencement of a game input using a player interface, the bet subtracted from the credit balance. A symbol selector selects symbols for display in the plurality of standard symbol positions and, dependent on the amount wagered, further arranged to select and display symbols in the additional symbol position(s) to increase the probability of a win outcome being generated. An outcome determiner determines an outcome of the game based on the displayed symbol positions.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 13, 2018
    Assignee: ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LIMITED
    Inventor: Claudio Daniel Dias Pires
  • Patent number: 9909980
    Abstract: A fluid analyzer includes a substrate, a quantum cascade laser formed on a surface of the substrate and including a first light-emitting surface and a second light-emitting surface facing each other, a first quantum cascade detector formed on the surface and including the same layer structure as the quantum cascade laser and a first light incident surface facing the first light-emitting surface, a second quantum cascade detector formed on the surface and including the same layer structure as the quantum cascade laser and a second light incident surface facing the second light-emitting surface, and a resin member covering at least the second light-emitting surface and the second light incident surface and having optical transparency and an electrical insulation property. A first space in which a fluid to be analyzed is disposed is provided in a first area between the first light-emitting surface and the first light incident surface.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: March 6, 2018
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Akio Ito, Tatsuo Dougakiuchi, Tadataka Edamura
  • Patent number: 9764942
    Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 19, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Antti Iihola, Altti Torkkeli, Ville-Pekka Rytkönen, Matti Liukku
  • Patent number: 9647425
    Abstract: A refractive index of the active layer is obtained by a photoluminescence inspection and an equivalent refractive index of the optical semiconductor element is computed. A refractive index of the optical waveguide layer is obtained by a photoluminescence inspection and an equivalent refractive index of the optical waveguide is computed. A film thickness of the refractive index adjustment layer is adjusted by etching the refractive index adjustment layer so that the equivalent refractive index of the optical semiconductor element and the equivalent refractive index of the optical waveguide are matched to each other. After adjusting the film thickness of the refractive index adjustment layer, a contact layer is formed on the second cladding layer and the refractive index adjustment layer. The optical waveguide is a passive waveguide to which no electrical field is applied and no current is injected.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 9, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naoki Nakamura
  • Patent number: 9583518
    Abstract: A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 28, 2017
    Assignee: LG Display Co., Ltd.
    Inventor: HyunSeok Hong
  • Patent number: 9490137
    Abstract: A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: November 8, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Simon Armbruster, Frank Fischer, Johannes Baader, Rainer Straub
  • Patent number: 9254864
    Abstract: The invention relates to a motor vehicle power steering mechanism having four groups of MOSFETs, in which with respect to the direct current voltage vehicle electrical system the MOSFETs of the first group (20) and of the second group (21) are arranged with their parasitic diodes in the reverse direction and the MOSFETs of the third group (31) and/or of the fourth group (30) are arranged with their parasitic diodes in the forward direction.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 9, 2016
    Assignee: ThyssenKrupp Presta AG
    Inventor: Gergely Dzsudzsak
  • Patent number: 9209091
    Abstract: A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 8, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: David Harper, Sudarsan Uppili, Fanling Hsu Yang, David L. Snyder, Christopher S. Blair, Guillaume Bouche
  • Patent number: 9182543
    Abstract: An optical integrated circuit may include a substrate including a single crystalline semiconductor material, a passive element extending in a <100> crystal orientation of the substrate and including the single crystalline semiconductor material, and an active element extending in a <110> crystal orientation of the substrate and including the single crystalline semiconductor material.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Gu Kim, Dong-Jae Shin, Yong-Hwack Shin, Young Choi, Kyoung-Ho Ha
  • Patent number: 9110233
    Abstract: A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation <110> and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation <010>.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Chul Kim, Bong-Jin Kuh, Jung-Yun Won, Eun-Ha Lee, Han-Mei Choi
  • Patent number: 9054162
    Abstract: A method is disclosed for forming conductive vias in a substrate by filling preformed via holes, preferably through via holes, with conductive material. The method includes providing a plurality of preformed objects at least partly including ferromagnetic material on a surface of the substrate; providing a magnetic source on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: June 9, 2015
    Inventors: Andreas Fischer, Göran Stemme, Frank Niklaus
  • Patent number: 9048179
    Abstract: Systems and methods for preparing films using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure and including ions having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include the ions being covalently bonded to each other, to the embedded structure, or to the substrate, whereas the ions instead may be free to diffuse through the substrate in the absence of the embedded structure. The embedded structure may inhibit or impede the ions from diffusing through the substrate, such that the ions instead covalently bond to each other, to the embedded structure, or to the substrate. The film may include, for example, diamond-like carbon, graphene, or SiC having a pre-selected phase.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: June 2, 2015
    Assignee: The Aerospace Corporation
    Inventors: Margaret H. Abraham, David P. Taylor
  • Publication number: 20150146275
    Abstract: An electro-optic modulator including a semiconductor region, a first reflecting region over the semiconductor region and an anti-reflecting region on an opposite surface of the semiconductor region from the first reflecting layer. The semiconductor region includes a first doped region and a second doped region.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu LEE, Ying-Hao KUO
  • Publication number: 20150148643
    Abstract: There is herein described light emitting medical devices and a method of manufacturing said medical devices. More particularly, there is described integrated light emitting medical devices (e.g. neural devices) capable of being used in optogenetics and a method of manufacturing said medical devices.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 28, 2015
    Applicant: MLED Limited
    Inventors: James Small, James Ronald Bonar, Zheng Gong, John Gareth Valentine, Erdan Gu, Martin David Dawson
  • Patent number: 9018646
    Abstract: A photoconductor comprising a layer stack with a semiconductor layer photoconductive for a predetermined wavelength range between two semiconductor boundary layers with a larger band gap than the photoconductive semiconductor layer on a substrate, wherein the semiconductor boundary layers comprise deep impurities for trapping and recombining free charge carriers from the photoconductive semiconductor layer, and two electrodes connected to the photoconductive semiconductor layer, for lateral current flow between the electrodes through the photoconductive semiconductor layer.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: April 28, 2015
    Assignee: Fraunhofer-Gesellschaft zur Foederung der angewandten Forschung e.V.
    Inventors: Bernd Sartorius, Harald Kuenzel, Helmut Roehle, Klaus Biermann
  • Publication number: 20150108507
    Abstract: A backside illuminated image sensor includes a semiconductor layer having a back-side surface and a front-side surface. The semiconductor layer includes a pixel array region including a plurality of photodiodes configured to receive image light through the back-side surface of the semiconductor layer. The semiconductor layer also includes a peripheral circuit region including peripheral circuit elements for operating the plurality of photodiodes that borders the pixel array region. The peripheral circuit elements emit photons. The peripheral circuit region also includes a doped semiconductor region positioned to absorb the photons emitted by the peripheral circuit elements to prevent the plurality of photodiodes from receiving the photons.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: OmniVision Technologies, Inc.
    Inventors: Qingfei Chen, Qingwei Shan, Yin Qian, Dyson H. Tai
  • Patent number: 9006709
    Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of an n-type, a second semiconductor layer of a p-type, and a light emitting unit. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer includes a nitride semiconductor. The light emitting unit is provided between the first semiconductor layer and the second semiconductor layer. The light emitting unit includes a plurality of well layers stacked alternately with a plurality of barrier layers. The well layers include a first p-side well layer most proximal to the second semiconductor layer, and a second p-side well layer second most proximal to the second semiconductor layer. A localization energy of excitons of the first p-side well layer is smaller than a localization energy of excitons of the second p-side well layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Patent number: 8987017
    Abstract: This disclosure discloses a method of manufacturing a light-emitting device, comprising proving a single growth substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface, wherein the light-emitting stacks are electrically connected to each other in series via a first electrical connecting structure; forming an electronic device on the second major surface; and forming a second electrical connecting structure extending from the first major surface to the second major surface and electrically connecting the first light-emitting stacks and the electronic device, wherein the electronic device comprises a resistance, an inductance, capacitance, or a rectifying device, and wherein the material of the resistance comprises tantalum nitride (TaN), silicon-chromium alloy (SiCr), or nickel-chromium alloy (NiCr).
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 24, 2015
    Assignee: Epistar Corporation
    Inventor: Chia-Liang Hsu
  • Patent number: 8981580
    Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Yu-Wen Liu, Hao-Yi Tsai, Hsien-Wei Chen
  • Publication number: 20150055910
    Abstract: A hybrid MOS optical modulator. The optical modulator includes an optical waveguide, a cathode comprising a first material and formed in the optical waveguide, and an anode comprising a second material dissimilar from the first material and formed in the optical waveguide, the anode adjoining the cathode, a capacitor being defined between the anode and the cathode.
    Type: Application
    Filed: April 30, 2012
    Publication date: February 26, 2015
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Di Liang
  • Publication number: 20150043319
    Abstract: An near-field light device (100) is provided with: a first electrode layer (123) having a protruding portion (123a); a second electrode layer (121); and a light emitting layer (122), the protruding portion protrudes along a predetermined direction (Y axis direction) to be capable of extracting energy which is caused by emission of light at the light emitting layer, the predetermined direction intersects with a laminated direction (X axis direction) of the near-field light device, an edge surface of at least one portion of the projection portion is located at more outward side in the optical device than an edge surface of the second electrode layer is.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Inventors: Takayuki KASUYA, Satoshi SUGIURA
  • Publication number: 20150041655
    Abstract: Optopair for use in sensors and analyzers of gases such as methane, and a fabrication method therefor is disclosed. It comprises: a) an LED, either cascaded or not, having at least one radiation emitting area, whose spectral maximum is de-tuned from the maximum absorption spectrum line of the gas absorption spectral band; and b) a Photodetector, whose responsivity spectral maximum can be either de-tuned from, or alternatively completely correspond to the maximum absorption spectrum line of the absorption spectral band of the gas. Modeling the LED emission and Photodetector responsivity spectra and minimizing the temperature sensitivity of the optopair based on the technical requirements of the optopair signal registration circuitry, once the spectral characteristics of the LED and Photodetector materials and the temperature dependencies of said spectral characteristics are determined, provides the LED de-tuned emission and Photodetector responsivity target peaks respectively.
    Type: Application
    Filed: May 2, 2014
    Publication date: February 12, 2015
    Applicant: BAH HOLDINGS LLC
    Inventors: MICHAEL TKACHUK, Sergey Suchalkin
  • Publication number: 20150028434
    Abstract: A resonant transducer includes a silicon single crystal substrate, a silicon single crystal resonator disposed over the silicon single crystal substrate, a shell made of silicon, surrounding the resonator with a gap, and forming a chamber together with the silicon single crystal substrate, an exciting module configured to excite the resonator, a vibration detecting module configured to detect vibration of the resonator, a first layer disposed over the chamber, the first layer having a through-hole, a second layer disposed over the first layer, a third layer covering the first layer and the second layer, and a projection extending from the second layer toward the resonator, the projection being spatially separated from the resonator, the projection being separated from the first layer by a first gap, the second layer being separated from the first layer by a second gap, the first gap is communicated with the second gap.
    Type: Application
    Filed: July 21, 2014
    Publication date: January 29, 2015
    Applicant: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Takashi YOSHIDA, Shuuji OKUDA, Shigeto IWAI
  • Patent number: 8940552
    Abstract: This invention discloses methods and apparatus to form organic semiconductor transistors upon three-dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three-dimensional surfaces with organic semiconductor-based thin film transistors, electrical interconnects, and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments, the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 27, 2015
    Assignee: Johnson & Johnson Vision Care, Inc.
    Inventors: Randall B. Pugh, Frederick A. Flitsch
  • Patent number: 8942520
    Abstract: In the optical waveguide board, simultaneously with pattern formation of mirror members at arbitrary positions on a clad layer 11, guiding patterns 14 having convex shapes are formed respectively at arbitrary positions on peripheral parts of mirror patterns 13, and the mirror patterns 13 are worked into tapered shapes. Next, in a state that a mask member 100 having through holes at desired positions, and the guiding patterns 14 are guided by mating, a metal film is formed on surfaces of slope parts 22 of the mirror patterns and the guiding patterns 14. Furthermore, in a state that the guiding patterns 14 and the photomask 16 are guided, wiring core patterns 20 are formed on the clad layer 11 adjacent to the mirror patterns 13.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: January 27, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yasunobu Matsuoka, Toshiki Sugawara
  • Patent number: 8940560
    Abstract: The present invention relates to a touching-type electronic paper and method for manufacturing the same. The touching-type electronic paper includes a TFT substrate and a transparent electrode substrate which are disposed as a cell. The transparent electrode substrate includes a common electrode, microcapsule electronic ink and light guiding poles as light transmitting passages, all of which are formed on a first substrate. The TFT substrate comprises displaying electrodes, first TFTs for driving the displaying electrodes, second TFTs for detecting lights transmitting through the light guiding poles and for producing level signals, and third TFTs for reading the level signals and sending the level signals to a back-end processing system, all of which are formed on a second substrate. The light guiding poles are opposite to the second TFTs respectively.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: January 27, 2015
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Zenghui Sun, Wenjie Hu, Zhuo Zhang, Gang Wang, Xibin Shao
  • Publication number: 20150023627
    Abstract: A method for producing a semiconductor optical device includes the steps of forming first and second optical waveguides; forming a first resin layer on the first and the second optical waveguides; forming an opening in the first resin layer; forming a first electrode in the opening; forming a second resin layer on the first electrode and the first resin layer; forming a groove in the second resin layer on the first electrode; forming a second electrode on the second resin layer, a side surface of the groove, and the top surface of the first electrode; and forming a third electrode on the second electrode. The second and third electrodes have a region in which the second and third electrodes pass over the second optical waveguide, and, in the region, the first and second resin layers are disposed between the second electrode and the second optical waveguide.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 22, 2015
    Inventors: Daisuke KIMURA, Hideki YAGI, Takamitsu KITAMURA
  • Patent number: 8936951
    Abstract: Provided are a semiconductor laser and a method of manufacturing the same. The method includes: providing a substrate including a buried oxide layer; forming patterns, which includes an opening part to expose the substrate, by etching the buried oxide layer; forming a germanium single crystal layer in the opening part; and forming an optical coupler, which is adjacent to the germanium single crystal layer, on the substrate.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Gyungock Kim, Sang Hoon Kim, Ki Seok Jang, JiHo Joo
  • Patent number: 8936953
    Abstract: Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. In one embodiment, a cavity is formed on a substrate to contain an LED and phosphor layer. The substrate has a channel separating the substrate into a first portion containing the cavity and a second portion. A filler of encapsulant material or other electrically insulating material is molded in the channel. The first portion can serve as a cathode for the LED and the second portion can serve as the anode.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jonathon G. Greenwood
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Publication number: 20150008390
    Abstract: Integrated upconversion devices capable of upconverting incident visible to short wavelength infrared photons to visible photons are disclosed. The device may include a quantum dot-based photodiode and a light-emitting diode. The device may further include a gain element such as a thin-film transistor.
    Type: Application
    Filed: March 17, 2014
    Publication date: January 8, 2015
    Applicant: Research Triangle Institute
    Inventors: John Lewis, Ethan Klem
  • Patent number: 8927965
    Abstract: A light-receiving element includes a III-V group compound semiconductor substrate, a light-receiving layer having a type II multi-quantum well structure disposed on the substrate, and a type I wavelength region reduction means for reducing light in a wavelength region of type I absorption in the type II multi-quantum well structure disposed on a light incident surface or between the light incident surface and the light-receiving layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 6, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Iguchi, Hiroshi Inada
  • Patent number: 8927303
    Abstract: The present invention relates to a light-emitting diode (LED) and a method for manufacturing the same. The LED comprises an LED die, one or more metal pads, and a fluorescent layer. The characteristics of the present invention include that the metals pads are left exposed for the convenience of subsequent wiring and packaging processes. In addition, the LED provided by the present invention is a single light-mixing chip, which can be packaged directly without the need of coating fluorescent powders on the packaging glue. Because the fluorescent layer and the packaging glue are not processed simultaneously and are of different materials, the stress problem in the packaged LED can be reduced effectively.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 6, 2015
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Wei-Kang Cheng, Jia-Lin Li, Shyi-Ming Pan, Kuo-Chi Huang
  • Patent number: 8927998
    Abstract: An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 6, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: YoonHwan Woo, SunJung Lee
  • Patent number: 8921129
    Abstract: A donor substrate includes a base substrate; a light reflection layer on the base substrate and partially overlapping the base substrate; a light-to-heat conversion layer on the base substrate, and including a combination layer including an insulating material and a first metal material; and a transfer layer on the light-to-heat conversion layer. A ratio of the first metal material in the combination layer to the insulating material in the combination layer increases as a distance from the base substrate increases along a thickness direction of the light-to-heat conversion layer.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joon Gu Lee, Won Jong Kim, Ji Young Choung, Jin Baek Choi, Yeon Hwa Lee, Hyunsung Bang, Young-Woo Song
  • Patent number: 8912017
    Abstract: Methods for bonding semiconductor wafers requiring the transfer of electrical and optical signals between the bonded wafers and across the bonding interface. The methods incorporate the formation of both electrical and optical interconnect vias within the wafer bonding interface to transfer electrical and optical signals between the bonded wafers. The electrical vias are formed using multiplicity of metal posts each comprised of multiple layers of metal that are interfused across the bonding surface. The optical vias are formed using multiplicity of optical waveguides each comprised of a dielectric material that interfuses across the bonding interface and having an index of refraction that is higher than the index of refraction of the dielectric intermediary bonding layer between the bonded wafers. The electrical and optical vias are interspersed across the bonding surface between the bonded wafers to enable uniform transfer of both electrical and optical signals between the bonded wafers.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Hussein S. El-Ghoroury, Chih-Li Chuang, Kameshwar Yadavalli, Qian Fan
  • Patent number: 8900891
    Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: December 2, 2014
    Assignee: IMEC
    Inventors: Bartlomiej Jan Pawlak, Tom Janssens
  • Publication number: 20140346532
    Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.
    Type: Application
    Filed: October 24, 2013
    Publication date: November 27, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Gyungock KIM, Hyundai PARK, In Gyoo KIM, Sang Hoon KIM, Ki Seok JANG, Sang Gi KIM, Jiho JOO, Yongseok CHOI, Hyuk Je KWON, Jaegyu PARK, Sun Ae KIM, Jin Hyuk OH, Myung Joon KWACK
  • Patent number: 8895957
    Abstract: The present invention relates to a light emitting device. The light emitting device comprises a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein a side surface including the N-type or P-type semiconductor layer has a slope of 20 to 80° from a horizontal plane. Further, a light emitting device comprises a substrate formed with a plurality of light emitting cells each including an N-type semiconductor layer and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein the N-type semiconductor layer of one light emitting cell and the P-type semiconductor layer of another adjacent light emitting cell are connected to each other, and a side surface including at least the P-type semiconductor layer of the light emitting cell has a slope of 20 to 80° from a horizontal plane.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Seoul Viosys Co., Ltd
    Inventors: Jong Lam Lee, Jae Ho Lee, Yeo Jin Yoon, Eu Jin Hwang, Dae Won Kim
  • Patent number: 8889436
    Abstract: A method for manufacturing optoelectronic devices comprising the steps of: providing a common growth substrate; forming a light-emitting epitaxy structure on the common growth substrate; forming a stripping layer on the light-emitting epitaxy structure; forming a solar cell epitaxy structure on the stripping layer; forming an adhesive layer on the solar cell epitaxy structure; proving a solar cell permanent substrate on the adhesive layer; and removing the stripping layer to form a light-emitting device and a solar cell device separately.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 18, 2014
    Assignee: Epistar Corporation
    Inventors: Wu-Tsung Lo, Yu-Chih Yang, Rong-Ren Lee
  • Patent number: 8883526
    Abstract: An image pickup device, wherein a part of the carriers overflowing from the photoelectric conversion unit for a period of photoelectrically generating and accumulating the carriers may be flowed into the floating diffusion region, and a pixel signal generating unit generating a pixel signal according to the carriers stored in the photoelectric conversion unit and the carriers having overflowed into the floating diffusion region, is provided. The expansion of a dynamic range and the improvement of an image quality can be provided by controlling a ratio of the carriers flowing into the floating diffusion region to the carriers overflowing from such a photoelectric conversion unit at high accuracy.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: November 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Okita, Toru Koizumi, Isamu Ueno, Katsuhito Sakurai
  • Publication number: 20140307997
    Abstract: Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.
    Type: Application
    Filed: December 20, 2011
    Publication date: October 16, 2014
    Inventors: Hanan Bar, John Heck, Avi Feshali, Ran Feldesh
  • Patent number: 8852983
    Abstract: A method for fabrication of capacitive environment sensors is provided in which the sensor elements are integrated in a CMOS structure with electronics through the use of complementary metal oxide semiconductor (CMOS) fabrication methods. Also provided are environment sensors fabricated, for example, by the method, and a measurement system using the environment sensors fabricated by the method. The described method includes etching away one of the metal layers in a CMOS chip to create a cavity. This cavity is then filled with an environment-sensitive dielectric material to form a sensing capacitor between plates formed by the metal adhesion layers or an array of contacts from other metal layers of the CMOS structure. This approach provides improved sensing capabilities in a system that is easily manufactured.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: October 7, 2014
    Assignee: Carnegie Mellon University
    Inventors: Gary Keith Fedder, Nathan Scott Lazarus
  • Patent number: 8847243
    Abstract: A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 30, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Emmanuelle Vigier-Blanc
  • Patent number: RE45217
    Abstract: A semiconductor light emitting device and a fabrication method thereof includes: providing a substrate; forming an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer on the substrate; forming a first transparent electrode having holes per a certain region on the p-type semiconductor layer; and forming a first pad on the first transparent electrode. A method of fabricating a semiconductor light emitting device, and which includes forming a light emitting layer on the first type semiconductor layer; forming a second type semiconductor layer on the light emitting layer; forming a first transparent electrode on the second type semiconductor layer, the first transparent electrode having holes per a certain region to thereby expose the second type semiconductor layer; forming a second transparent electrode on the first transparent electrode; forming a first pad on the second transparent electrode; and forming a second pad over the first type semiconductor layer.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 28, 2014
    Assignee: LG Electronics Inc.
    Inventors: Jun-Seok Ha, Jun-Ho Jang, Jae-Wan Choi, Jung-Hoon Seo