Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/25)
  • Patent number: 11409059
    Abstract: Structures and methods for passively aligning a photonic die with a receiving substrate are described. Three alignment surfaces, having dimensions greater than a desired alignment accuracy, may be formed on the photonic die and used to passively and accurately align the photonic die to a receiving substrate in six degrees of freedom. Two of the three alignment surfaces on the photonic die may be formed in a single mask-and-etch process, while the third alignment surface may require no patterning or etching. Three complementary alignment surfaces on the receiving substrate may be formed in a single mask-and-etch process.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: August 9, 2022
    Assignee: Acacia Communications, Inc.
    Inventors: Diedrik Vermeulen, Christopher Doerr
  • Patent number: 11402591
    Abstract: An optical coupling device of an embodiment includes: a first lead frame; a light emitting element provided on the first lead frame; a second lead frame; a light receiving element provided on the second lead frame and facing the light emitting element; a polyimide resin covering a light emitting surface of the light emitting element; a transparent resin portion provided between the light emitting element and the light receiving element; and a light-shielding resin molded body accommodating the light emitting element and the light receiving element.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 2, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takamitsu Noda, Yoshiko Takahashi
  • Patent number: 11335656
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11282911
    Abstract: Display devices, display modules, and methods of manufacture are disclosed. In one example, a display device includes a pixel region in which pixels for displaying an image are arranged, on an upper surface of a substrate. A device-side signal electrode for exchanging a signal related to the pixels with an outside is disposed on a side surface of the substrate. A module casing is configured to store the display device and to have a casing-side signal electrode electrically connected to the device-side signal electrode in a spot facing the device-side signal electrode.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: March 22, 2022
    Assignee: Sony Group Corporation
    Inventors: Hiroshi Horikoshi, Masato Kawashima, Kaori Takimoto, Masaya Nagata
  • Patent number: 10993317
    Abstract: An optical module may be formed on a wafer. The wafer may include a substrate and one or more optical components encapsulated, at least partially, by the substrate. Each of the optical components are configured to emit or sense light. The wafer may also include one or more printed circuit board (PCB) bars encapsulated, at least partially, by the substrate allowing electrical conductivity from a first side of the substrate to a second side of the substrate. The wafer may also include at least one redistribution layer to electrically couple at least one of the optical components to at least one of the PCB bars.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Apple Inc.
    Inventors: Yinjuan He, Karthik Shanmugam, Peter R. Harper, Tongbi Tom Jiang
  • Patent number: 10784241
    Abstract: Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 22, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: HanBeet Chang, EunSung Shin, HyunYong Cho
  • Patent number: 10607973
    Abstract: Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 31, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: HanBeet Chang, EunSung Shin, HyunYong Cho
  • Patent number: 10490712
    Abstract: Light emitter packages, components, and related methods for providing improved chemical resistance are provided herein. In one aspect, a component of a light emitter package is provided. The component can include a base material, a silver (Ag) containing material at least partially disposed over the base material, and a portion of phenyl containing silicone encapsulant at least partially disposed over the Ag portion. The component can be incorporated within a surface mount device (SMD) type light emitter package.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 26, 2019
    Assignee: Cree, Inc.
    Inventors: Shaow B. Lin, Christopher P. Hussell
  • Patent number: 10263138
    Abstract: The present invention provides a micro light-emitting-diode display panel and a manufacturing method thereof. The micro light-emitting-diode display panel which presses and fixes the micro light-emitting-diodes into a resin adhesive layer by filling the resin adhesive layer in the pixel groove. Meanwhile, the electrode at the bottom of the micro light-emitting-diode is guided to the top of the micro light-emitting-diode by the connection electrode, making the two electrodes of the micro light-emitting-diode are at the top, to facilitate the connection between the electrodes of the micro light-emitting-diode and the electrode points, which can reduce the difficulty of the electrode bonding of the micro light-emitting-diode, and improve the reliability of the electrode bonding of the micro light-emitting-diode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 16, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Macai Lu
  • Patent number: 10199412
    Abstract: This disclosure describes optoelectronic modules that include an image sensor having at least two regions separated optically from one another by a wall. The wall can include a bridge portion that extends over the image sensor and further can include a cured adhesive portion, part of which is disposed between a lower surface of the bridge portion and an upper surface of the image sensor. Various techniques are described for fabricating the modules so as to help prevent the adhesive from contaminating sensitive regions of the image sensor. The wall can be substantially light-tight so as to prevent undesired optical cross-talk, for example, between a light emitter located to one side of the wall and a light sensitive region of the image sensor located to the other side of the wall.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 5, 2019
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Simon Gubser, Sonja Hanselmann, Qichuan Yu, Cris Calsena, Guo Xiong Wu, Hartmut Rudmann
  • Patent number: 10177257
    Abstract: A thin film transistor, a method for fabricating the same, a display substrate, and a display device are disclosed. The method comprises: forming in sequence a light shielding layer, an insulating layer, and a semiconductor layer; and forming a pattern of the light shielding layer, the insulating layer, and the semiconductor layer in one patterning process. A polycrystalline silicon layer can be formed into an active layer and an amorphous silicon layer into the light shielding layer, by using only one mask. The number of masking processes is reduced by one, which simplifies a fabricating process of the thin film transistor.
    Type: Grant
    Filed: February 14, 2016
    Date of Patent: January 8, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shi Shu, Bin Zhang, Chuanxiang Xu, Yonglian Qi
  • Patent number: 10062675
    Abstract: Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled.
    Type: Grant
    Filed: June 4, 2017
    Date of Patent: August 28, 2018
    Assignee: LUMENS CO., LTD.
    Inventors: HanBeet Chang, EunSung Shin, HyunYong Cho
  • Patent number: 9920488
    Abstract: Systems and methods for automated repair and maintenance operations on a railroad track comprise a work head that is automatically moved over the railroad track according to a predetermined pattern, such as the movement of an applicator for tie plugging compound according to a predetermined pattern of spike holes. The automated repair and maintenance operations may be coupled to systems and methods for automatically detecting a feature on a railroad track that comprise two or more distance measurement sensors that travel over the railroad track. Features on the railroad track are detected where the distance measured by each sensor falls within two different predetermined distance ranges.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 20, 2018
    Assignee: Encore Rail Systems, Inc.
    Inventors: Douglas Delmonico, Stephen R. Epps, Brandon H. Long, Jacob Schmidt
  • Patent number: 9865577
    Abstract: A display and method of manufacture are described. The display may include a substrate including an array of pixels with each pixel including multiple subpixels, and each subpixel within a pixel is designed for a different color emission spectrum. An array of micro LED device pairs are mounted within each subpixel to provide redundancy. An array of wavelength conversion layers comprising phosphor particles are formed over the array of micro LED device pairs for tunable color emission spectrum.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 9, 2018
    Assignee: APPLE INC.
    Inventors: Andreas Bibl, Kelly McGroddy
  • Patent number: 9420700
    Abstract: An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An inclined paddle sawn flat no-leads (IPSFN) package may be affixed to a cover glass surface along a perimeter of a display. IPSFN packages may incorporate a photo-emitter chip and a photo-detector chip that may be inclined for a desired angle of incidence relative to the cover glass. A CMOS integrated optical transceiver package may include inclined photonic chips and a non-inclined CMOS chip having at least one of a photo-emitter driver, or a photo-detector TIA and/or ADC. A chip package lead frame may include cantilevered paddle tabs amenable to controlled deflection during package assembly. An inclined packaging assembly method may include attaching a chip to a lead frame paddle and form pressing the lead frame to incline the chip to a desired angle before encapsulation.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Gerrit J Vreman, Tom E Pearson, Peter L Chang, Jia-Hung Tseng
  • Patent number: 9360644
    Abstract: A multi semiconductor device package includes a laser die and a photonics die. The laser die generates light and includes a laser facet that emits light from a light emitting surface. The photonics die modulates light emitted from the laser light emitting surface and includes a device side cavity that exposes an embedded waveguide optically connected with the laser facet. A laser die and photonics die attachment method includes positioning a device side of the laser die relative to a device side of the photonics die, engaging an alignment feature of the photonics die with an alignment feature of the laser die, installing the laser die within a device side recess of photonics die, electrically connecting the laser die with the photonics die, and optically connecting a laser facet of the laser die with an embedded waveguide of the phonics die.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 7, 2016
    Assignee: International Business Machines Corporation
    Inventors: Benjamin V. Fasano, Paul F. Fortier
  • Patent number: 9304256
    Abstract: An apparatus may be provided. The apparatus may comprise a first edge having a first area and a second edge having a second area larger than the first area. The apparatus may further comprise a volume of material disposed between the first edge and the second edge. The volume of material may have a first numeral aperture value at the first area and a second numeral aperture value at the second area. The second numeral aperture value may be less than the first numeral aperture value.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 5, 2016
    Assignee: Cisco Technology, Inc.
    Inventor: D. Brice Achkir
  • Patent number: 9293449
    Abstract: Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou-Cheng Hu, Chen-Shien Chen, Tin-Hao Kuo, Chih-Hua Chen, Ching-Wen Hsiao
  • Patent number: 9277657
    Abstract: A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 1, 2016
    Assignee: Kyocera SLC Technologies Corporation
    Inventors: Hiroyuki Fukushima, Fumio Kumokawa
  • Patent number: 9249014
    Abstract: An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 2, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Khalil Hosseini, Joachim Mahler, Georg Meyer-Berg
  • Patent number: 9236521
    Abstract: An optocoupler having optical lens layer is disclosed. The optocoupler may comprise an optical emitter, an optical receiver, an isolation layer, a lens layer and a substantially transparent encapsulant. The lens layer may be integrally formed within the optical receiver. Alternatively, the lens layer may be formed integrally with the isolation layer, or the lens layer may be an optical film attached on the optical receiver. The substantially transparent encapsulant may encapsulate at least partially the optical emitter, the optical receiver and the isolation layer. The isolation layer may be inserted to the substantially transparent encapsulant, making the substantially transparent encapsulant into two compartments. In another embodiment, an electronic system having optocoupler is disclosed.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: January 12, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Thiam Siew Tay, Premkumar Jeromerajan
  • Patent number: 9108841
    Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Publication number: 20150145078
    Abstract: A semiconductor package includes a semiconductor die having a first main side and a second main side opposite the first main side, the first main side having an inner region surrounded by a periphery region. The semiconductor package further includes a film covering the semiconductor die and adhered to the periphery region of the first main side of the semiconductor die. The film has a curved surface so that the inner region of the first main side of the semiconductor die is spaced apart from the film by an air gap. Electrical conductors are attached at a first end to pads at the periphery region of the first main side of the semiconductor die. A corresponding method of manufacture is also provided.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventor: Chee Yang Ng
  • Patent number: 9041045
    Abstract: A transparent LED wafer module and a method for manufacturing the same are provided. In a conductor LED device epitaxial process, the conductor LED device is grown on a transparent material wafer, where both surfaces of the conductor LED device are entirely grown on the transparent material, and then a transparent glass substrate is restacked, thereby securing a high amount of light.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: May 26, 2015
    Inventor: Sung-Bok Shin
  • Publication number: 20150137148
    Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an optical package that includes a stacked arrangement with a plurality of optical devices arranged over an image sensor processor die that is coupled to a first substrate. Between the two optical devices and the image sensor processor die there is provided at least a second substrate. In one embodiment, the optical package is a proximity sensor package and the optical devices include a light-emitting diode die and a light-receiving diode die. In one embodiment, the light-emitting diode die is secured to a surface of the second substrate and the light-receiving diode die is secured to a surface of a third substrate. The second and the third substrate may be secured to a surface of the image sensor processor die or to a surface of encapsulation material.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Wing Shenq Wong
  • Publication number: 20150137285
    Abstract: A capacitive micromachined ultrasonic transducer and a method of fabricating the same are provided. The capacitive micromachined ultrasonic transducer includes a device substrate including a first trench defining a plurality of first portions corresponding to an element and a second trench spaced apart from the first trench; a supporting unit provided on the device substrate, the supporting unit defining a plurality of cavities; a membrane provided on the supporting unit to cover the plurality of cavities; a top electrode electrically connected to a second portion in the second trench through a via hole penetrating through the membrane and the supporting unit; and a through silicon via (TSV) substrate provided on a bottom surface of the device substrate, the TSV substrate including a first via metal connected to the plurality of first portions corresponding to the element and a second via metal connected to the second portion.
    Type: Application
    Filed: May 23, 2014
    Publication date: May 21, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-sik SHIM, Seog-woo HONG, Seok-whan CHUNG, Chang-jung KIM
  • Patent number: 9036959
    Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Marwan H. Khater, Edward W. Kiewra, Steven M. Shank
  • Publication number: 20150129841
    Abstract: A method and apparatus for an OLED display system is presented. A substrate is provided and a display is provided on the substrate. At least one sensor is also provided on the substrate. A barrier is provided on the substrate between the display and said the least one sensor, the barrier blocking emissions from the display from being sensed by the at least one sensor.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: Bose Corporation
    Inventor: Mark R. Hickman
  • Publication number: 20150131941
    Abstract: A method for producing an optical assembly includes the steps of forming an optical semiconductor device including a substrate, a recess and an first optical waveguide, the optical semiconductor device having a principal surface, the recess extending from the principal surface to a middle portion of the substrate; forming an optical waveguide device including a through-hole and a second optical waveguide; positioning the optical semiconductor device and the optical waveguide device so that the principal surface of the optical semiconductor device and a back surface of the optical waveguide device face each other; aligning the optical semiconductor device and the optical waveguide device by inserting a guide pin into the through-hole and the recess so that the first optical waveguide is optically coupled with the second optical waveguide; and joining the optical semiconductor device and the optical waveguide device to each other.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Applicant: Sumitomo Electric Industries, LTD.
    Inventor: Akira FURUYA
  • Publication number: 20150123157
    Abstract: A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.
    Type: Application
    Filed: September 10, 2014
    Publication date: May 7, 2015
    Applicant: Skorpios Technologies, Inc.
    Inventors: John Dallesasse, Stephen B. Krasulick, Timothy Creazzo, Elton Marchena
  • Publication number: 20150118770
    Abstract: A semiconductor device package is formed by mounting a semiconductor die on an adhesive tape substrate, mounting a sacrificial structure on the adhesive tape substrate, applying molding material on the adhesive tape substrate to embed the die and at least a portion of the at least one sacrificial structure; removing the adhesive tape substrate to define a package assembly, forming a redistribution layer on a surface of the package assembly, and removing sacrificial material to form a void in the molding material having a shape corresponding to a shape of the sacrificial material that was removed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Detlef Krabe, Martin Weigert
  • Publication number: 20150115038
    Abstract: The invention relates to a transponder layer (10), in particular for producing a chip card, having an antenna substrate (12), which, on an antenna side (11), is equipped with an antenna (14) formed from a wire conductor (13), and has a chip accommodation which is formed by a recess in the antenna substrate and in which a chip (21) is accommodated, wherein wire conductor ends, which serve to form terminal ends (15) of the antenna, are formed at a bottom (20) of the chip accommodation which is recessed with respect to the rear side (26) of the antenna substrate (12), and the chip is accommodated in the chip accommodation in such a manner that terminal contacts (22) arranged on a contact side (36) of the chip are contacted with flat contact portions (19) of the terminal ends (15), and the chip is arranged with the rear side (27) of its semiconductor body (28) facing the terminal contacts substantially flush with the rear side of the antenna substrate.
    Type: Application
    Filed: April 4, 2013
    Publication date: April 30, 2015
    Applicant: Smartrac IP B.V.
    Inventors: Martin Kuschewski, Manfred Rietzler
  • Patent number: 9018040
    Abstract: A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Publication number: 20150111324
    Abstract: A package structure of an optical module is provided and includes: a light-emitting chip and a light-admitting chip which are disposed at a light-emitting region and a light-admitting region of a substrate, respectively; two encapsulants for enclosing the light-emitting chip and the light-admitting chip, respectively, and forming hemispherical first and second lens portions above the light-emitting chip and the light-admitting chip, respectively; a cover disposed on the substrate and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively, and the first and second lens portions are received in the light-emitting hole and the light-admitting hole, respectively.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Ming-Te TU, Yao-Ting YEH
  • Publication number: 20150108506
    Abstract: During a fabrication technique, trenches are defined partially through the thickness of a substrate. Then, photonic integrated circuits are coupled to the substrate. These photonic integrated circuits may be in a diving-board configuration, so that they at least partially overlap the trenches. While this may preclude the use of existing dicing techniques, individual hybrid integrated photonic chips (which each include a portion of the substrate and at least one of the photonic integrated circuits) may be singulated from the substrate by: coupling a carrier to a front surface of the substrate; thinning the substrate from a back surface until the partial trenches are reached (for example, by grinding the substrate); attaching a support mechanism (such as tape) to the back surface of the substrate; removing the carrier; and then removing the support mechanism.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: Oracle International Corporation
    Inventors: Chaoqi Zhang, Hiren D. Thacker, Ashok V. Krishnamoorthy
  • Patent number: 9012949
    Abstract: A highly reliable light-emitting module or light-emitting device is provided. A method for manufacturing a highly reliable light-emitting module is provided. The light-emitting module includes, between a first substrate and a second substrate, a first electrode provided over the first substrate, a second electrode provided over the first electrode with a layer containing a light-emitting organic compound interposed therebetween, and a sacrifice layer formed using a liquid material provided over the second electrode.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideto Ohnuma, Hajime Kimura, Yasuhiro Jinbo
  • Patent number: 9012264
    Abstract: An integrated circuit package is provided with a thin-film battery electrically connected to and encapsulated with an integrated circuit die. The battery can be fabricated on a dedicated substrate, on the die pad, or on the integrated circuit die itself.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Michael J. Hundt, Haibin Du, Krishnan Kelappan, Frank Sigmund
  • Publication number: 20150104129
    Abstract: An optical module includes: at least one optical waveguide provided on a surface of a substrate; a plurality of grooves provided in the optical waveguide on the surface of the substrate and having both a surface orthogonal to the surface of the substrate and an inclined surface; multiple pairs of light-emitting and light-receiving elements aligned with the plurality of grooves in the optical waveguide and provided so as to correspond to light of different wavelengths on the optical waveguide; and a plurality of light-selecting filters each provided on an inclined surface of the plurality of grooves in the optical waveguide and reflecting light of the wavelength corresponding to the light-emitting element in the respective pair of light-emitting and light-receiving elements towards the optical waveguide, and selectively reflecting light of the corresponding wavelength from the light propagating through the optical waveguide towards the corresponding pair of light-emitting and light-receiving elements.
    Type: Application
    Filed: September 11, 2014
    Publication date: April 16, 2015
    Inventors: Shigeru Nakagawa, Yoichi Taira, Masao Tokunari
  • Patent number: 9006750
    Abstract: An optical semiconductor package has a base material that includes a principal surface, an optical semiconductor element that is located on the principal surface of the base material to project or receive light, and an optical transparency sealing layer that seals the optical semiconductor element while covering the principal surface of the base material. An air gap having a shape surrounding an optical axis of the optical semiconductor element is provided in the optical transparency sealing layer such that the light is reflected by an interface of a portion corresponding to an inner circumferential surface of the air gap in an interface formed by the air gap and the optical transparency sealing layer.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: April 14, 2015
    Assignee: OMRON Corporation
    Inventors: Satoshi Hirono, Manabu Ikoma, Naoto Inoue, Tsuyoshi Miyata, Kazunari Komai
  • Publication number: 20150097778
    Abstract: An optical sensing module includes an image sensing element having an optical sensor array and at least a control unit. A light emitting chip provides a coherent light. The light is reflected from an outside surface and to be received by the optical sensor array. A substrate is mounted with the image sensing element and the light emitting chip. A cover is mounted on the substrate to cover the image sensing element and the light emitting chip, and the cover includes a first light-transmitting portion on the transmission path of the light. The optical sensing module is disposed on a base having a second light-transmitting portion on the transmission path of the light.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Inventors: YUN-SHAN CHANG, DA-WEI LIN
  • Patent number: 9000702
    Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: April 7, 2015
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Tsing Hsu
  • Patent number: 8987017
    Abstract: This disclosure discloses a method of manufacturing a light-emitting device, comprising proving a single growth substrate having a first major surface and a second major surface; forming a plurality of light-emitting stacks on the first major surface, wherein the light-emitting stacks are electrically connected to each other in series via a first electrical connecting structure; forming an electronic device on the second major surface; and forming a second electrical connecting structure extending from the first major surface to the second major surface and electrically connecting the first light-emitting stacks and the electronic device, wherein the electronic device comprises a resistance, an inductance, capacitance, or a rectifying device, and wherein the material of the resistance comprises tantalum nitride (TaN), silicon-chromium alloy (SiCr), or nickel-chromium alloy (NiCr).
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 24, 2015
    Assignee: Epistar Corporation
    Inventor: Chia-Liang Hsu
  • Patent number: 8980654
    Abstract: The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 17, 2015
    Assignee: SEN Corporation
    Inventors: Shiro Ninomiya, Akihiro Ochi
  • Patent number: 8975098
    Abstract: A method of manufacturing a semiconductor light emitting element includes preparing a semiconductor stacked layer structure by stacking a first semiconductor layer and a second semiconductor layer in this order, forming a second electrode and an insulating layer in this order on the second semiconductor layer, exposing the first semiconductor layer by removing a part of the second semiconductor layer, forming a first electrode by forming a metal layer on the exposed first semiconductor layer and the insulating layer and flattening a surface of the metal layer, forming a first electrode-side bonding layer having a top layer made of Au on the first electrode, preparing a support substrate including a support substrate-side bonding layer having a top surface made of Au, and bonding the first electrode-side bonding layer and the support substrate-side bonding layer.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: March 10, 2015
    Assignee: Nichia Corporation
    Inventors: Hiroaki Matsumura, Takashi Abe, Kyosuke Nakagawa
  • Patent number: 8975099
    Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Jun Adachi, Jun Urakawa, Issei Yamamoto
  • Publication number: 20150064817
    Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.
    Type: Application
    Filed: October 31, 2014
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Raghavasimhan Sreenivasan
  • Publication number: 20150060891
    Abstract: An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: STMicroelectronics Pte Ltd.
    Inventor: Yonggang Jin
  • Publication number: 20150054001
    Abstract: A camera module and method of making same, includes a substrate of conductive silicon having top and bottom surfaces, a sensor device, and an LED device. The substrate includes a first cavity formed into the bottom surface of the substrate and has an upper surface, an aperture extending from the first cavity upper surface to the top surface of the substrate, and a second cavity formed into the top surface of the substrate and having a lower surface. The sensor device includes at least one photodetector, is disposed at least partially in the first cavity, and is mounted to the first cavity upper surface. The LED device includes at least one light emitting diode, is disposed at least partially in the second cavity, and is mounted to the second cavity lower surface.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Vage Oganesian, Zhenhua Lu
  • Patent number: 8962357
    Abstract: A method of manufacturing an organic light emitting diode (OLED) display according to an exemplary embodiment includes: forming a display unit displaying an image and a driver positioned near the display unit to drive a light emitting element of the display unit in a lower mother substrate; forming a sealant and a plurality of bumps in an upper mother substrate; aligning the lower mother substrate and the upper mother substrate to face each other; melting and hardening the sealant to combine the lower mother substrate and the upper mother substrate; cutting the upper mother substrate; and cutting the lower mother substrate, wherein the cutting of the upper mother substrate is performed according to a first cutting line between the sealant and the bumps and a second cutting line corresponding to the bumps.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Seop Park
  • Patent number: 8962359
    Abstract: In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 24, 2015
    Assignee: Crystal IS, Inc.
    Inventors: Leo J. Schowalter, Jianfeng Chen, James R. Grandusky