Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract: The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact.

Abstract: In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the oxide film. A light transmission and/or absorption film is formed over the oxide film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light from above the light transmission and/or absorption film to form a ferroelectric film.

Abstract: According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant.

Abstract: Semiconductor capacitors comprise first electrodes, second electrodes, and tantalum oxide layers positioned between the first electrodes and the second electrodes. The tantalum oxide layers are formed by depositing at least one precursor and ozone gas, the at least one precursor represented by the formula: wherein X is selected from the group consisting of nitrogen, sulfur, oxygen, and a carbonyl group; and wherein R1 and R2 are independently alkyl.

Abstract: A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.

Abstract: The invention includes chemical vapor deposition and physical vapor deposition methods of forming high k ABO3 comprising dielectric layers on a substrate, where “A” is selected from the group consisting of Group IIA and Group IVB elements and mixtures thereof, and where “B” is selected from the group consisting of Group IVA metal elements and mixtures thereof. In one implementation, a plurality of precursors comprising A, B and O are fed to a chemical vapor deposition chamber having a substrate positioned therein under conditions effective to deposit a high k ABO3 comprising dielectric layer over the substrate. During the feeding, pressure within the chamber is varied effective to produce different concentrations of A at different elevations in the deposited layer and where higher comparative pressure produces greater concentration of B in the deposited layer.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: A ferroelectric or electret memory circuit, particularly a ferroelectric or electret memory circuit with improved fatigue resistance, including a ferroelectric or electret memory cell with a polymer or oligomer memory material contacting first and second electrodes, at least one of the electrodes is comprised of at least one functional material capable of physical and/or chemical bulk incorporation of atomic or molecular species contained in either the electrode or the memory material and displaying a propensity for migrating in the form of mobile charged and/or neutral particles between an electrode and a memory material, something which can be detrimental to both. A functional material with the above-mentioned properties shall serve to offset any adverse effect of a migration of this kind, leading to an improvement in the fatigue resistance of the memory cell.

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Abstract: A capacitor is provided that is optimal for use in DRAM and has high dielectric constant, and allows leakage current flowing therethrough to be maintained at a low level, and further, permits dependence of the leakage current on temperatures to be small. That is, capacitor openings are formed in an inter layer silicon oxide layer and a TiN film is patterned so that TiN films are left only within the openings to form lower electrodes within the openings. Subsequently, a Zr- and/or Hf-containing oxide film (represented by the formula, multicomponent Zr.sub.x.Hf.sub.1-x.O.sub.2 film (0?x?1)) formed from a metal-containing organic compound as a reactant and a Ti-containing oxide film are laminated to form capacitor dielectrics.

Abstract: In an electrode drying process in which the electrode is molded in a sheet shape by kneading activated carbon powder, a binding material and an organic solvent for lubrication and a polarizing property electrode is formed by heating and removing the organic solvent for lubrication in the molded electrode, the organic solvent for lubrication included in the electrode is removed in a state in which the above electrode is widened in the sheet shape. In a manufacturing method of an electrode sheet for the electrical double layer capacitor, continuous drying and vacuum drying are performed in a drying process.

Abstract: A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: There are provided the steps of forming a first insulating film over a semiconductor substrate, forming a capacitor having a lower electrode, a ferroelectric layer, and an upper electrode over the first insulating film, and growing a second insulating film over the first insulating film and the capacitor by using a mixed gas containing a compound gas of oxygen and nitrogen, TEOS, and oxygen. Accordingly, characteristics of the capacitor can be improved irrespective of the capacitor forming position on the insulating layer.

Abstract: A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric layer sandwiched between the top electrode and a bottom electrode. The top electrode is patterned according to the pattern of the hardmask by etching at a first temperature. The top electrode serves as the noble metal hardmask and the ferroelectric layer is patterned according to the pattern of the top electrode at a second temperature lower than the first temperature, resulting in the top electrode having sidewalls beveled relative to a top surface of the top electrode etching. The bottom electrode is etched at a third temperature to form the capacitor.

Abstract: A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.

Abstract: Disclosed is a method of manufacturing a MIM (metal-insulator-metal) capacitor using copper as a lower electrode. The MIM capacitor is manufactured by the following processes. A lower copper electrode is formed on a substrate. A photoresist pattern having a capacitor hole through which the lower copper electrode is exposed, is then formed. Next, the surface of the photoresist pattern is hardened to form a photoresist hardening layer. Thereafter, a capacitor dielectric film and an upper electrode material layer are formed on the photoresist hardening layer including the capacitor hole. The upper electrode material layer and the capacitor dielectric film are then polished by means of chemical mechanical polishing process to form an upper electrode within the capacitor hole. Finally, the photoresist pattern including the photoresist hardening layer is removed. As such, the MIM capacitor is manufactured without using the mask process and the etch process.

Abstract: Low cross talk resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises a bit formed using a perovskite material interposed at a cross point of an upper electrode and lower electrode. Each bit has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit, decrease the resistivity of the bit, or determine the resistivity of the bit. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.

Abstract: A method of forming a capacitor includes forming a conductive metal first electrode layer over a substrate, with the conductive metal being oxidizable to a higher degree at and above an oxidation temperature as compared to any degree of oxidation below the oxidation temperature. At least one oxygen containing vapor precursor is fed to the conductive metal first electrode layer below the oxidation temperature under conditions effective to form a first portion oxide material of a capacitor dielectric region over the conductive metal first electrode layer. At least one vapor precursor is fed over the first portion at a temperature above the oxidation temperature effective to form a second portion oxide material of the capacitor dielectric region over the first portion. The oxide material of the first portion and the oxide material of the second portion are common in chemical composition. A conductive second electrode layer is formed over the second portion oxide material of the capacitor dielectric region.

Abstract: Methods are provided for fabricating semiconductor structures and semiconductor device structures utilizing epitaxial Hf3Si2 layers. A process in accordance with one embodiment of the invention begins by disposing a silicon substrate in a processing chamber. The pressure within the processing chamber and a temperature of the silicon substrate in the range of approximately 250° C. to approximately 700° C. is established. A layer of Hf3Si2 then is grown overlying the silicon substrate at a rate in the range of about one (1) to about five (5) monolayers per minute.

Abstract: The present invention relates to a method for manufacturing a ferroelectric field-effect transistor, particularly to a ferroelectric field-effect transistor with a metal/ferroelectric/insulator/semiconductor (MFIS) gate capacitor structure. The method comprises steps of depositing a bismuth layered ferroelectric film on the insulator buffered Si, after a high-temperature thermal treatment, depositing an upper electrode on the bismuth layered ferroelectric film.

Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

Abstract: The method for manufacturing an FeRAM capacitor having an enhanced adhesive property between a dielectric layer and a bottom electrode and a grain uniformity of the dielectric layer, is employed by forming hillocks on the bottom electrode purposefully before formation of the dielectric layer. The method includes steps of: preparing an active matrix obtained by predetermined processes; forming a first bottom electrode on the active matrix; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on a top face of the bottom electrode; carrying out a first annealing process for deforming a surface of the second bottom electrode; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the third ILD; carrying out a second annealing process; and forming a top electrode on the dielectric layer.

Abstract: A method of fabricating an integrated circuit device having capacitors is provided. The capacitors can include a first electrode, a dielectric layer and a second electrode. An interlayer insulating layer is formed on the capacitor. The interlayer insulating layer is patterned to form a metal contact hole that exposes a region of the second electrode. The exposed region of the second electrode is reduced to remove excessive oxygen atoms that can exist in the second electrode.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material. In one embodiment, the composite dielectric layer includes a substantially uniform layer of the reaction product of the first dielectric material and the second dielectric material.

Abstract: A semiconductor device includes an interlevel insulating film, a contact plug, a barrier film, a first electrode, a capacitor insulating file, and a second electrode. The interlevel insulating film is formed on a semiconductor substrate. The contact plug extends through the interlevel insulating film and is formed from a conductive material. The barrier film is formed from a tungsten-based material on the upper surface of the contact plug. The first electrode is connected to the contact plug via the barrier film and formed from a metal material on the interlevel insulating film. The capacitor insulating film is formed from an insulating metal oxide on the first electrode. The second electrode is insulated by the capacitor insulating film and formed on the surface of the first electrode.

Abstract: A magnetic element which can switch states using a relatively lower magnetic field. The magnetic element comprises first and second magnetic layers separated by an intermediate layer. The magnetization of the first magnetic layer is fixed in a first direction parallel to the easy axis. The second magnetic layer comprises first and second magnetization vectors which are in opposite directions to create a magnetic boundary therein. The magnetic boundary can be driven out of the second magnetic layer by shifting the boundary along a first or second direction along the easy axis.

Abstract: The present invention provides embodiments of methods and devices for the suppression of copper hillocks. Copper hillocks are suppressed by capping the copper layer with a dielectric film before any significant growth of copper hillocks can begin using a ramped temperature dielectric deposition process. Copper hillocks are also suppressed by doping a copper layer with a dopant that will constrain the grain size of the copper during subsequent processing. These methods are applicable to the construction of MIM capacitors and interconnect structures.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxides formed from elements such as yttrium and gadolinium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile ferroelectric memory device can include first and second split wordlines formed along a first direction on a substrate at prescribed intervals, a first electrode of a first ferroelectric capacitor on the second split wordline and a first electrode of a second ferroelectric capacitor on the first split wordline, first and second ferroelectric layers respectively on surfaces of the first electrodes of the first and second ferroelectric capacitors, and second electrodes of the first and second ferroelectric capacitors, respectively, on surfaces of the first and second ferroelectric layers.

Abstract: The invention achieves the fine processing of an information writing device, which includes a multilayered element obtained by stacking ferromagnetic/semiconductor/ferromagnetic layers, without increasing the resistivity and power consumption of the device and lowering the reliability thereof. The invention provides an information storage apparatus (1) having write word lines (11), bit lines (21) formed in such a way as to intersect with the write word lines (11) at predetermined intervals, and information storage devices (31) each comprising a multilayered film including a magnetic layer provided in an intersection region, in which each of the write word lines (11) intersects with an associated one of the bit lines (21), between the write word lines (11) and the bit lines (21).

Abstract: A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: The present invention relates to a method for fabricating a ferroelectric memory device. The method includes the steps of: forming a first insulation layer on a substrate; forming a storage node contact contacting to a partial portion of the substrate by passing through the first insulation layer; forming a stack pattern of a lower electrode contacting to the storage node contact and a hard mask on the first insulation layer; forming a second insulation layer on an entire surface of the resulting structure including the stack pattern; planarizing the second insulation layer until a surface of the hard mask is exposed; removing selectively the exposed hard mask to make a surface level of the lower electrode lower than that of the second insulation layer; and forming sequentially a ferroelectric layer and an upper electrode on the second insulation layer and the lower electrode.

Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

Abstract: A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.

Abstract: A ferroelectric capacitor is provided in which the surface area of a ferroelectric thin film is expanded to increase the amount of polarization.

Abstract: The method for manufacturing a DRAM capacitor is employed to enhance charge capacitance and electrical endurance of the DRAM capacitor by structuring a double dielectric layer of aluminum oxide (Al2O3) and hafnium oxide (HfO2). The method includes steps of: preparing an active matrix including a semiconductor substrate, an ILD formed on the semiconductor substrate and a storage node obtained after patterning the ILD into a predetermined configuration; forming a bottom electrode on top faces of the storage node and portions of the ILD; forming a diffusion barrier on an exposed surface of the bottom electrode; forming a double dielectric layer including an aluminum oxide layer and a hafnium oxide layer, wherein the aluminum oxide layer and the hafnium oxide layer are formed on the diffusion barrier in succession; carrying out an annealing process for recovering dielectric properties of the aluminum oxide layer and the hafnium oxide layer; and forming a top electrode on the hafnium oxide layer.

Abstract: The method for manufacturing an FeRAM capacitor having an enhanced adhesive property between a dielectric layer and a bottom electrode and a grain uniformity of the dielectric layer, is employed by forming hillocks on the bottom electrode purposefully before formation of the dielectric layer. The method includes steps of: preparing an active matrix obtained by predetermined processes; forming a first bottom electrode on the active matrix; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on a top face of the bottom electrode; carrying out a first annealing process for deforming a surface of the second bottom electrode; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the third ILD; carrying out a second annealing process; and forming a top electrode on the dielectric layer.

Abstract: High density oxide films are deposited by a pulsed-DC, biased, reactive sputtering process from a titanium containing target to form high quality titanium containing oxide films. A method of forming a titanium based layer or film according to the present invention includes depositing a layer of titanium containing oxide by pulsed-DC, biased reactive sputtering process on a substrate. In some embodiments, the layer is TiO2. In some embodiments, the layer is a sub-oxide of Titanium. In some embodiments, the layer is TixOy wherein x is between about 1 and about 4 and y is between about 1 and about 7. In some embodiments, the layer can be doped with one or more rare-earth ions. Such layers are useful in energy and charge storage, and energy conversion technologies.

Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: A magnetic memory cell that uses a curved magnetic region to create magnetic anisotropy is provided by the present invention. The magnetic memory cell is created from a free magnetic layer, a barrier layer and a reference magnetic layer. The magnetic layers are constructed such that they have portions that are curved with respect to a first axis and straight with respect to a second perpendicular axis. These curved portions result in a magnetic memory cell that has an easy axis that is parallel to the first axis and a hard axis that is perpendicular to the easy axis. In addition, the resulting magnetic memory cell's coercivity is independent of it's thickness. Thus, the magnetic memory cell is well adapted to being scaled down without increasing the likelihood of thermally induced errors.

Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.