Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract: A method for manufacturing a ferroelectric capacitor includes successively disposing a lower electrode, at least one intermediate electrode and an upper electrode over a base substrate, and providing ferroelectric films between the electrodes, respectively. In the step of forming the intermediate electrode, (a) a first metal film is formed by a sputter method over the ferroelectric film, and (b) a second metal film is formed by a vapor deposition method over the first metal film.

Abstract: A method is provided for manufacturing a capacitor including the steps of forming a lower electrode on a substrate, forming an insulation film formed of a perovskite type metal oxide on the lower electrode, and forming an upper electrode on the insulation film. The step of forming the insulation film includes the steps of coating a dispersion liquid in which fine crystal powder of a second metal oxide of a perovskite type in a liquid containing a precursor compound of a first metal oxide of a perovskite type on the lower electrode, and performing a heat treatment of the dispersion liquid after coating.

Abstract: In a ferroelectric element, the ferroelectric film is prevented from deteriorating and the interconnect film from lowering in reliability. A ferroelectric element includes a first electrode, a ferroelectric film formed on the first electrode, a second electrode formed on the ferroelectric film, a first hydrogen blocking film formed directly on a surface of the second electrode, a first insulation film formed on the first hydrogen blocking film, a first opening formed in the first hydrogen blocking film exposing a part of the second electrode, a second opening formed in the first insulation film and having a greater diameter than the diameter of the first opening, and an interconnect film connected to the second electrode through the first and second openings.

Abstract: The present invention provides a substrate having thereon a patterned small molecule organic semiconductor layer. The present invention also provides a method and a system for the production of the substrate having thereon a patterned small molecule organic semiconductor layer. The substrate with the patterned small molecule organic semiconductor layer is prepared by exposing a region of a substrate having thereon a film of a precursor of a small organic molecule to energy from an energy source to convert the film of a precursor of a small organic molecule to a patterned small molecule organic semiconductor layer.

Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap

Abstract: A method of manufacturing an ultra-thin PZT pyrochlore film comprises providing a structure comprising a base layer, and forming on the base layer, a titanium layer and a PZT layer in mutual contact. The structure is annealed to form a PZT pyrochlore layer on said base layer. Novel devices with an ultra-thin PZT layer may thereby be manufactured.

Abstract: A dielectric film containing HfO2/ZrO2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO2. A gate dielectric is formed by atomic layer deposition of HfO2 using a HfI4 precursor followed by the formation of ZrO2 on the HfO2 layer.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: (a) forming a first inter-level insulating film on a semiconductor substrate formed with semiconductor elements; (b) forming a contact hole through the first inter-level insulating film; (c) forming a plug made of conductive material capable of being nitrided, the plug being embedded in the contact hole; and (d) heating the semiconductor substrate in a nitriding atmosphere to nitride the plug from a surface thereof. This semiconductor device manufacture method can prevent breakdown of a plug when a capacitor is formed on the plug.

Abstract: As a method for fabricating a semiconductor device, a lower electrode is first formed on a semiconductor substrate and then a first ferroelectric film is formed on the lower electrode by CVD using a first source gas. Thereafter, a second ferroelectric film is formed on the first ferroelectric film by CVD using a second source gas. Subsequently, an upper electrode is formed on the second ferroelectric film. In this method, the concentration of bismuth contained in the first source gas is different from the concentration of bismuth contained in the second source gas.

Abstract: The present disclosure provides an improved magnetic memory cell. The magnetic memory cell includes a switching element and two magnetic tunnel junction (MTJ) devices. A conductor connects the first and second MTJ devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element. The resistance of the first MTJ device is different from the resistance of the second.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: The invention includes semiconductor devices. In one implementation, semiconductor device includes a first conductive material. A first layer of a dielectric material is over the first conductive material. A second layer of the dielectric material is on the first layer. A second conductive material is over the second layer of the dielectric material. A device in accordance with an implementation of the invention can include a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: A miniaturized imaging device and method of viewing small luminal cavities are described. The imaging device can be used as part of a catheter, and can include a lens, an SSID including an imaging array optically coupled to the lens; an umbilical including a conductive line; and an adaptor configured to support the lens and provide electrical communication between the SSID and conductive line. Alternatively, the adaptor can be a rigid adaptor configured to provide electrical communication between the SSID and the conductive line through a conductive path. The conductive path can be configured along multiple contiguous surfaces of the adaptor such that the SSID is electrically coupled to the conductive path at a first surface, and the conductive line is electrically coupled to the conductive path at a second surface.

Abstract: A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second monolayers comprising tantalum and oxygen and the other of the first and second monolayers comprising oxygen and another element different from tantalum. A dielectric layer can be formed containing the first and second monolayers. The dielectric layer can exhibit a dielectric constant greater than the first monolayer. The another element can include a Group IB to VIIIB element, such as titanium and/or zirconium. The forming of the first and second monolayer can include atomic layer depositing. A dielectric material can include first and second chemisorbed materials, the second material containing oxygen and a Group IB to VIIIB element and the dielectric material exhibiting a dielectric constant greater than the first chemisorbed material. The dielectric material can further exhibit less current leakage than the first material.

Abstract: The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

Abstract: An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.

Abstract: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.

Abstract: A method of fabricating a ferroelectric capacitor that can inhibit ferroelectric characteristics from deteriorating includes forming a lower electrode film over from on a top surface of a plug disposed in a silicon oxide film to on the silicon oxide film; forming a paraelectric film so as to frame-likely cover a periphery of a surface of the lower electrode film with a predetermined width; forming a ferroelectric film over from on the exposed lower electrode film from an opening of the paraelectric film to on the paraelectric film in the surroundings of the exposed lower electrode film; forming an upper electrode film, in a surface of the ferroelectric film, over from on a region that faces a contact surface between the lower electrode film and the ferroelectric film to on a region that faces the paraelectric film; and etching through a mask that covers, in a surface of the upper electrode film, from a region that faces the contact surface to a region that faces the paraelectric film.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film 9, 10 above a semiconductor substrate 1; forming a capacitor Q having a lower electrode 11a, a dielectric film 13a, and an upper electrode 14c on the first insulating film 9, 10; forming a second insulating film 15, 15a, 16 coating the capacitor Q; and forming a stress-controlling insulating film 30 on the rear surface of the semiconductor substrate 1 after the second insulating film 15, 15a, 16 have been formed.

Abstract: A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed over the first capacitor electrode material. The semiconductor substrate with silicon nitride comprising layer is provided within a chamber. An oxygen comprising plasma is generated remote from the chamber. The remote plasma generated oxygen is fed to the semiconductor substrate within the chamber at a substrate temperature of no greater than 750° C. effective to form a silicon oxide comprising layer over the silicon nitride comprising layer. After the feeding, a second capacitor electrode material is formed over the silicon oxide comprising layer. Methods of forming capacitor dielectric layers are also disclosed.

Abstract: A method of forming a ferroelectric thin film on a high-k layer includes preparing a silicon substrate; forming a high-k layer on the substrate; depositing a seed layer of ferroelectric material at a relatively high temperature on the high-k layer; depositing a top layer of ferroelectric material on the seed layer at a relatively low temperature; and annealing the substrate, the high-k layer and the ferroelectric layers to form a ferroelectric thin film.

Abstract: Capacitors of semiconductor devices and methods of fabricating the same are disclosed. An example capacitor-fabricating method comprises: forming a first insulating layer by nitrifying a semiconductor substrate; forming a second insulating layer by depositing a transition element on the first insulating layer and performing a reoxidation process; forming a third insulating layer by nitrifying the second insulating layer using a forming gas; and forming a conducting layer on top of the third insulating layer.

Abstract: In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

Abstract: An ALD method deposits conformal tantalum-containing material layers on small features of a substrate surface. The method includes the following principal operations: depositing a thin conformal and saturated layer of tantalum-containing precursor over some or all of the substrate surface; using an inert gas or hydrogen plasma to purge the halogen byproducts and unused reactants; reducing the precursor to convert it to a conformal layer of tantalum or tantalum-containing material; using another purge of inert gas or hydrogen plasma to remove the halogen byproducts and unused reactants; and repeating the deposition/reduction cycles until a desired tantalum-containing material layer is achieved. An optional step of treating each newly formed surface of tantalum containing material with a nitrogen-containing agent can be added to create varying amounts of tantalum nitride.

Abstract: Multi-layered structures formed using atomic-layer deposition processes include multiple metal oxide layers wherein the metal oxide layers are formed without the presence of interlayer oxide layers and may include different metal oxide compositions.

Abstract: In a method for forming a ferroelectric film of insulating metal oxide on a surface of an electrode with a concave or a convex or in convex shape which is formed above a substrate, multiple types of source gases constituting a material gas and each containing an organometallic compound are introduced into a chamber and main components of the multiple types of source gases are allowed to chemically react with one another with the chemical reaction proceeding depending on the reaction rate. Then, the ferroelectric film is deposited on the surface of the electrode.

Abstract: A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating.

Abstract: Dielectric layers containing a chemical vapor deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Forming a layer of hafnium oxide by chemical vapor deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon dioxide. Forming the layer of hafnium oxide by chemical vapor deposition using precursors that do not contain carbon permits the formation of the dielectric layer without carbon contamination. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.

Abstract: The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal and one or more of carbon, boron and nitrogen, and the metal oxide of the dielectric material can comprise the same metal as the barrier layer. The dielectric material/barrier layer constructions can be incorporated into capacitors. The capacitors can be used in, for example, DRAM cells, which in turn can be used in electronic systems.

Abstract: A semiconductor device is provided which has a capacitor insulating film made up of zirconium aliminate being an amorphous film obtained by having crystalline dielectric contain amorphous aluminum oxide and having its composition of AlXZr(1-X)OY (0.05?X?0.3), hereby being capable of preventing, in a process of forming a capacitor of MIM (Metal Insulator Metal) structure, dielectric breakdown of a capacitor insulating film while a relative dielectric constant of a metal oxide film used as the capacitor insulating film is kept high.

Abstract: A manufacturing method according to the present invention of a solid electrolytic capacitor includes: a step of immersing a anode body on which the dielectrics film layer is formed in a solution that includes from 0.7 to 10% by weight of hydrogen peroxide, from 0.3 to 3% by weight of sulfuric acid and water as a main solvent, followed by, after pulling up, exposing to vapor of pyrrole or a pyrrole derivative, and thereby forming, on the dielectrics film layer, a first conductive polymer layer made of polypyrrole or a polypyrrole derivative; and a step of immersing the anode body on which the dielectrics film layer and the first conductive polymer layer are formed in a solution that includes a polymerizing monomer and a supporting electrolyte to electrolytically polymerize the polymerizing monomer, and thereby forming a second conductive polymer layer on the first conductive polymer layer.

Abstract: This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.

Abstract: A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.

Abstract: A fabrication of a capacitor in a semiconductor is simplified by using nitrogen plasma in forming an aluminum nitride layer functioning as an insulation layer on the aluminum layer disposed in a capacitor region. Subsequently, a planarized IMD (inter-metal dielectric) layer is obtained, facilitating via etching process.

Abstract: A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more silicon precursor compounds of the formula Si(OR)4 with one or more zirconium and/or hafnium precursor compounds of the formula M(NR?R?)4, wherein R, R?, and R? are each independently an organic group and M is zirconium or hafnium.

Abstract: Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such method and structure may use a Group VIII metal as an etch stop or end point for the planarization process with subsequent etching to remove undesired portions of the Group VIII metal. One exemplary method of providing a conductive material in an opening includes providing a substrate assembly having at least one surface and providing an opening defined through the surface of the substrate assembly. The opening is defined by at least one surface. At least one conductive material (e.g., at least one Group VIII metal such platinum and/or rhodium) is formed within the opening on the at least one surface defining the opening and on at least a portion of the substrate assembly surface. A support film (e.g., an oxide material) is formed over the conductive material and a fill material (e.g.

Abstract: Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed.

Abstract: A method of forming a dielectric film by an organic metal CVD method, comprising the step of supplying an organic metal compound into a treating container having a substrate to be treated held therein to form the dielectric film on the substrate, wherein the dielectric film forming step comprises the first step of depositing, in the treating container, the dielectric film under a first condition so set as to allow the residence time of the organic metal compound to extend to a first value, and the second step of further depositing, after the first step and in the treating container, the dielectric film under a second condition so set as to allow the residence time of the organic metal compound to extend to a second value smaller than the first value.

Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.

Abstract: A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer layer disposed between the lower electrode and the thin dielectric layer, the buffer layer including a metal oxide of Group 3, 4, or 13. In an embodiment, the method of fabricating includes absorbing CO on a surface of a lower electrode of a platinum group metal, placing the lower electrode under a reducing atmosphere to produce a lattice oxygen, using the lattice oxygen to form a thin dielectric layer by performing an ALD process using a precursor for the thin dielectric layer, and forming an upper electrode of a platinum group metal on the thin dielectric layer.

Abstract: A semiconductor device having a gate electrode on a silicon substrate via a gate insulating film is formed by laminating the gate insulating film with a silicon oxide film, formed on the silicon substrate, an Hf silicate film is formed on the silicon oxide film, and a nitrogen-containing Hf silicate film formed on the Hf silicate film, and containing Hf in a peak concentration in a range from one atomic % to thirty atomic %, and nitrogen in a peak concentration in a range from ten atomic % to thirty atomic %.

Abstract: Disclosed is a capacitor with a dielectric structure having an aluminum oxide layer and a lanthanum oxide layer and a fabrication method thereof. The capacitor includes: a lower electrode; a first dielectric layer with a high energy band gap formed on the lower electrode; a second dielectric layer formed on the first dielectric layer, the second dielectric layer with a high dielectric constant, wherein an energy band gap of the second dielectric layer is lower than the energy band gap of the first dielectric layer; and an upper electrode formed on the second dielectric layer.

Abstract: A method of making a film with a high dielectric constant uses a spin-on sol-gel process to deposit the film on a substrate, the film having a composition (SiO2)x(TiO2)1?x, where 0.50<x<0.75. The resulting film is annealed in an oxygen-containing atmosphere at a temperature lying in the range of 500° C. to 700° C.

Abstract: A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.

Abstract: A method of producing a ferroelectric capacitor includes preparing a semiconductor substrate having MOSFETs with an impurity diffused area in a memory cell area and a peripheral circuit area; forming a first interlayer insulating film on the semiconductor substrate; forming a conductive plug in the first interlayer insulating film to be electrically connected to the impurity diffused area; forming a second interlayer insulating film on the first interlayer insulating film; removing a portion of the second interlayer insulating film in the memory cell area to expose the first interlayer insulating film and the conductive plug; laminating a first conductive layer, a ferroelectric layer, and a second conductive layer sequentially on the first interlayer insulating film and the second interlayer insulating film to form a capacitor forming laminated film; forming an etching mask on the capacitor forming laminated film; and etching the capacitor forming laminated film to form a ferroelectric capacitor.

Abstract: A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved ALCVD). Then, a high dielectric constant (high k) dielectric layer is formed overlying the collar dielectric and the bottom portion of the deep trench using atomic layer chemical vapor deposition (ALCVD). Thereafter, a conductive layer is filled into the deep trench and recessed to a predetermined depth. A portion of the dielectric layer and the high dielectric constant (high k) layer at the top of the deep trench are removed to complete the fabrication of the deep trench capacitor.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.