Capacitor Patents (Class 438/239)
  • Patent number: 11367725
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 21, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 11315932
    Abstract: A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 26, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Shih-Chieh Lin, Shuen-Hsiang Ke
  • Patent number: 11283012
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 22, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: R. Stanley Williams
  • Patent number: 11264504
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 1, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yanping Shen, Haiting Wang, Hong Yu
  • Patent number: 11239205
    Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen
  • Patent number: 11211386
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, bit lines disposed on the dielectric layer, spacers and a contact. The substrate has active areas arranged in parallel with each other. The bit lines are arranged in parallel with each other. Each bit line is partially overlapped with the corresponding active area. Each bit line has first portions and second portions arranged alternately in an extending direction thereof, and a width of the first portions is smaller than that of the second portions. The spacers are disposed on the sidewalls of each bit line. The contact is disposed between the adjacent bit lines and adjacent to the corresponding first portion of at least one of the adjacent bit lines, penetrates through the dielectric layer, and is in contact with the corresponding active area.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 28, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Chih Hsu, Yi-Hao Chien, Huang-Nan Chen
  • Patent number: 11177264
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: November 16, 2021
    Inventors: Jae-hyeon Jeon, Se-keun Park, Dong-sik Park, Seok-ho Shin
  • Patent number: 11114481
    Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer has a thickness of 10 nm or more. The first electrode contains carbon. At the interface between the dielectric layer and the first electrode, an elemental percentage of carbon is 30 atomic % or less.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 7, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuuko Tomekawa, Takahiro Koyanagi, Takeyoshi Tokuhara
  • Patent number: 11088030
    Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Ru-Gun Liu, Sai-Hooi Yeong, Yen-Ming Chen, Yung-Sung Yen, Ying-Yan Chen
  • Patent number: 11081559
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 3, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Sivakumar Kumarasamy, George Pete Imthurn, Sinan Goktepeli
  • Patent number: 11011627
    Abstract: A semiconductor structure and a method for forming same, the forming method including: providing a base, where the base includes a device region for forming devices and isolation regions located on two sides of the device region; patterning the base to form a substrate and fins protruding from the substrate; forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and forming an isolation layer on the substrate exposed by the fins and the first dummy fins, where the isolation layer covers a part of side walls of the fin. In some implementations of the present disclosure, the setting of the first dummy fins improves the uniformity of pattern density in peripheral regions for each fin, which is advantageous for improving the thickness uniformity of an isolation layer in the device region, reducing the probability that the fin is bent or tilted, and improving electrical properties of the semiconductor structure.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 11004950
    Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
  • Patent number: 10998397
    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yi Chen, Chung-Chieh Yang, Yung-Chow Peng
  • Patent number: 10937817
    Abstract: An array substrate is provided. The array substrate includes a capacitor, which includes a plurality of metal electrodes arranged opposite to each other. The plurality of metal electrodes are spaced apart from each other in a horizontal direction parallel to a plane in which the array substrate is located, and an orthogonal projection of each of at least two of the plurality of metal electrodes of the capacitor on the plane in which the array substrate is located includes a curved portion.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Baoxia Zhang, Cuili Gai, Ling Wang
  • Patent number: 10916548
    Abstract: An apparatus can have first and second memory cells. The first memory cell can have a first storage device selectively coupled to a first digit line at a first level by a first vertical transistor at a second level. The second memory cell can have a second storage device selectively coupled to a second digit line at the first level by a second vertical transistor at the second level. A third digit line can be at a third level and can be coupled to a main sense amplifier. A local sense amplifier can be coupled to the first digit line, the second digit line, and the third digit line. The second level can be between the first and third levels.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Charles L. Ingalls
  • Patent number: 10854613
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 10811418
    Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: October 20, 2020
    Assignee: DOSILICON CO., LTD.
    Inventors: Jin Ho Kim, Tae Gyoung Kang
  • Patent number: 10734395
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Patent number: 10727232
    Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Arvind Kumar, Mahendra Pakala, Sanjeev Manhas, Satendra Kumar Gautam
  • Patent number: 10692978
    Abstract: According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 ?m or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 ?m or more.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 23, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhisa Nagao, Hidetoshi Abe
  • Patent number: 10685709
    Abstract: A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Masumi Saitoh
  • Patent number: 10629672
    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yi Chen, Chung-Chieh Yang, Yung-Chow Peng
  • Patent number: 10439132
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Patent number: 10224324
    Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Pi-Hsuan Lai
  • Patent number: 10192783
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 9991288
    Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 5, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9899372
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 9859242
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9559070
    Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yi-Wen Wu
  • Patent number: 9558949
    Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: January 31, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Michael Konevecki, Steve Radigan, Vance Dunton, Natalie Nguyen, Luke Zhang
  • Patent number: 9496267
    Abstract: In one device, a first space partitioned by first and second line patters is filled with a multilayer film that is composed of a first silicon film having a high impurity concentration relative to a standard plug impurity concentration and a second silicon film having a low impurity concentration relative to the standard plug impurity concentration, and is divided by forming a groove using a mask film on the side wall of the second line pattern. As a result, expansion of a seam, which is formed only on the second silicon film having a low impurity concentration, is suppressed. After that, an isolation insulating film is embedded in the groove and impurity diffusion is carried out by a heat treatment, so that divided plugs as a whole are made to have the standard plug impurity concentration.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 15, 2016
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Kazuaki Tonari, Yuki Togashi
  • Patent number: 9472557
    Abstract: A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Kazutaka Manabe
  • Patent number: 9461143
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 9449830
    Abstract: A method for fabricating a transistor that includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a first fluorine-free tungsten layer as an interface stabilization layer over the gate dielectric layer, forming a second fluorine-free tungsten layer as a barrier layer over the first fluorine-free tungsten layer, forming a bulk tungsten layer as a gate electrode over the second tungsten layer to fill the trench, and selectively recessing the third tungsten layer, the second tungsten layer and the first tungsten layer to form a buried gate structure.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 20, 2016
    Assignee: SK Hynix Inc.
    Inventor: Dong-Kyun Kang
  • Patent number: 9451131
    Abstract: A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: September 20, 2016
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Hiroshi Takahashi, Reijiroh Shohji
  • Patent number: 9419000
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Ji-young Kim
  • Patent number: 9388337
    Abstract: A light emitting element according to one embodiment of the present invention is configured of a metal fluoride crystal which is represented by chemical formula LiM1M2F6 (wherein Li includes 6Li; M1 represents at least one alkaline earth metal element selected from among Mg, Ca, Sr and Ba; and M2 represents at least one metal element selected from among Al, Ga and Sc), said metal fluoride crystal containing 0.02% by mole or more of Eu and having an Eu2+ concentration of less than 0.01% by mole.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 12, 2016
    Assignees: TOKUYAMA CORPORATION, TOHOKU UNIVERSITY
    Inventors: Sumito Ishizu, Kentaro Fukuda, Noriaki Kawaguchi, Akira Yoshikawa, Takayuki Yanagida, Yui Yokota, Yutaka Fujimoto
  • Patent number: 9343665
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
  • Patent number: 9343369
    Abstract: Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Du, Karim Arabi
  • Patent number: 9305927
    Abstract: A semiconductor device having a buried gate is provided. The semiconductor device is formed in a structure in which a plurality of contacts having small step differences are stacked without forming a metal contact applying an operation voltage to the buried gate in a single contact and a contact pad is formed between the contacts so that failure due to misalignment can be prevented without a separate additional process for forming the contacts.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Chul Hwan Cho
  • Patent number: 9305786
    Abstract: A semiconductor device using a small-sized metal contact as a program gate of an antifuse, and a method of fabricating the same are described. The semiconductor device includes a metal contact structure formed on a semiconductor substrate of a peripheral circuit area, and includes a first gate insulating layer to be ruptured. A gate structure is formed on the semiconductor substrate to one side of the metal contact structure.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: April 5, 2016
    Assignee: SK HYNIX INC.
    Inventor: Yong Sun Jung
  • Patent number: 9231081
    Abstract: In a method of manufacturing a semiconductor device, a body region is formed in an epitaxial layer provided on a semiconductor substrate. A part of a semiconductor material forming the body region surface is removed to form a convex-type contact region protruding from the body region surface and to form a shallow trench surrounding the convex-type contact region. A deep trench region is formed so as to extend from the shallow trench surface to inside of the epitaxial layer. A gate insulating film is formed on an inner wall of the deep trench region which is filled with polycrystalline silicon that is held in contact with the gate insulating film. A source region and a body contact region are formed in the shallow trench and the convex-type contact region, respectively, and a silicide layer is formed to connect the source region and the body contact region to each other.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 5, 2016
    Assignee: SEIKO INSTRUMENTS INC.
    Inventor: Naoto Saitoh
  • Patent number: 9195630
    Abstract: A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
  • Patent number: 9196620
    Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Min Park, Dae-Ik Kim
  • Patent number: 9184167
    Abstract: Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Zhimin Song, Che-Chi Lee, Brett Busch
  • Patent number: 9159732
    Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: October 13, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong-Han Shin, Jum-Yong Park
  • Patent number: 9117817
    Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 25, 2015
    Assignees: Auburn University, Rutgers, The State University of New Jersey
    Inventors: John R. Williams, Ayayi C. Ahyi, Tamara F. Isaacs-Smith, Yogesh K. Sharma, Leonard C. Feldman
  • Patent number: RE45702
    Abstract: The present invention provides a semiconductor device comprising: a silicon based semiconductor substrate provided with a step including an non-horizontal surface, a horizontal surface and a connection region for connecting the non-horizontal surface and the horizontal surface; a gate insulating film formed in at least a part of the step; and a gate electrode formed on the gate insulating film, wherein the entirety or a part of the gate insulating film is formed of a silicon oxynitride film that contains a rare gas element at a area density of 1010 cm?2 or more in at least a part of the silicon oxynitride film.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignees: SHARP KABUSHIKI KAISHA
    Inventors: Tadahiro Omi, Naoki Ueda
  • Patent number: RE46122
    Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Shigehiko Saida, Yoshitaka Tsunashima
  • Patent number: RE47227
    Abstract: A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 5, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Takeshi Ohgami