Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.

Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Abstract: A capacitor structure of memory is provided in the present invention, including structures of multiple cylindrical bottom electrode layers with bottoms contacting a substrate and extending vertically and upwardly from the substrate, the cylindrical shape of the bottom electrode layer has a sidewall with wavelike cross-section, and the wavelike cross-sections of adjacent bottom electrode layers are identical but shifted vertically by a distance, a capacitive dielectric layer on the bottom electrode layers, and a top electrode layer on the capacitive dielectric layer.

Abstract: A semiconductor device includes a memory cell storing data. The memory cell capacitor includes a plurality of bottom electrodes on a substrate and extending in a vertical direction with respect to a top surface of the substrate, the plurality of bottom electrodes being spaced apart from each other in a first direction parallel to the top surface of the substrate, an upper support pattern on upper lateral surfaces of the plurality of bottom electrodes, and a lower support pattern on lower lateral surfaces of the plurality of bottom electrodes. The lower support pattern is disposed between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes includes a first recess adjacent to a bottom surface of the lower support pattern.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Abstract: A spatial light modulator (SLM) is provided that includes an optical resonator (i.e., pixel) having nanoscale size. The optical resonator having nanoscale size includes a phase-change material such as, for example, a GeSbTe alloy, sandwiched between silicon nitride cladding layers. The phase-change material can undergo a crystalline-to-amorphous phase transition which is characterized by a large change in optical properties of the resonator.

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

Abstract: Provided is a semiconductor epitaxial wafer in which the concentration of hydrogen in a modifying layer can be maintained at a high level and the crystallinity of an epitaxial layer is excellent. A semiconductor epitaxial wafer has a semiconductor wafer, a modifying layer formed in a surface portion of the semiconductor wafer, which modifying layer has hydrogen contained as a solid solution in the semiconductor wafer, and an epitaxial layer formed on the modifying layer. The concentration profile of hydrogen in the modifying layer in the thickness direction from a surface of the epitaxial layer is a double peak concentration profile including a first peak shallower in the depth direction and a second peak deeper in the depth direction.

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Abstract: First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

Abstract: Embodiments of systems and methods for semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process. In an embodiment, a method includes receiving a substrate with a patterned structure formed on a surface of the substrate. A method may also include depositing a first interconnect material in a first region of the patterned structure. Such methods may also include depositing a second interconnect material in a second region of the patterned structure, wherein the first interconnect material is different from the second interconnect material, and wherein the first region and the second region include a common layer of the patterned structures.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.

Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.

Abstract: Methods and apparatuses for controlling aerosol streams being deposited onto a substrate via pneumatic shuttering. The aerosol stream is surrounded and focused by an annular co-flowing sheath gas in the print head of the apparatus. A boost gas flows to a vacuum pump during printing of the aerosol. A valve adds the boost gas to the sheath gas at the appropriate time, and a portion of the two gases is deflected in a direction opposite to the aerosol flow direction to at least partially prevent the aerosol from passing through the deposition nozzle. Some or all of the aerosol is combined with that portion of the boost gas and sheath gas and is exhausted from the print head. By precisely balancing the flows into and out of the print head, maintaining the flow rates of the aerosol and sheath gas approximately constant, and keeping the boost gas flowing during both printing and shuttering, the transition time between printing and partial or full shuttering of the aerosol stream is minimized.

Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.

Abstract: Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.

Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.

Abstract: Providing for improved manufacturing of silver-based electrodes to facilitate formation of a robust metallic filament for a resistive switching device is disclosed herein. By way of example, a silver electrode can be embedded with a non-silver material to reduce surface energy of silver atoms of a silver-based conductive filament, increasing structural strength of the conductive filament within a resistive switching medium. In other embodiments, an electrode formed of a base material can include silver material to provide mobile particles for an adjacent resistive switching material. The silver material can drift or diffuse into the resistive switching material to form a structurally robust conductive filament therein.

Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.

Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.

Abstract: A display device includes a display panel, a support frame including a plurality of straight portions located at two adjacent outer side surfaces of the display panel and having a substantially equal cross-section and a curved portion connecting the plurality of straight portions and having a curvature, a plurality of protrusion frames each extending from a straight portion of the plurality of straight portions of the support frame toward an inner portion of the display panel, and a mold portion overlapping the plurality of protrusion frames to be joined with the plurality of protrusion frames and being located along an inner surface of the curved portion of the support frame.

Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant, with a coolant temperature below ?20° C. An etch gas comprising a metal containing component, a carbon containing component, and a halogen containing component is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched in the stack with respect to the patterned mask.

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

Abstract: A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.

Abstract: A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

Abstract: The present invention relates to a network device, a terminal device, and a voice service control method, a frame type of voice data is determined, and therefore, a voice service of the network device may be disconnected when no speech frame time exceeds set time, which prevents an economic loss caused by a non-talking call maintained for a long time, thereby saving a resource of an operator network, and improving utilization efficiency of the operator network.

Abstract: The object of the invention is the provision of apparatuses and methods for stable direct printing of continuous films or discreet structures on a substrate using an internal pneumatic shutter. The invention uses an aerodynamic focusing technique, with a print head comprising an aerosolization source, a flow cell, an aerodynamic lens system, and a pneumatic shutter assembly. The method uses an interchangeable and variable aerodynamic lens system mounted in the flow cell, and an annularly flowing sheath gas to produce a highly collimated micrometer-size stream of aerosolized droplets. The lens system is comprised of a single-orifice or multi-orifice lens coupled to a converging fluid dispense nozzle. A liquid atomizer with temperature control is used to produce an aerosol size distribution that overlaps the functional range of the aerodynamic lens system. The shutter assembly can be attached directly to the print head, or mounted external to the print head in a control module.

Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.

Abstract: A capacitor for a semiconductor memory element includes a lower electrode, a dielectric layer disposed on the lower electrode and including titanium oxide, and an upper electrode disposed on the dielectric layer. The lower electrode includes a first metal and a second metal, the first metal including at least one selected from the group consisting of platinum (Pt), osmium (Os), rhodium (Rh) and palladium (Pd), the second metal including at least one selected from the group consisting of ruthenium (Ru) and iridium (Jr).

Abstract: A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.

Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm?3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm?3 or less.

Abstract: The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.

Abstract: Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.

Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.

Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.