Including Passive Device (e.g., Resistor, Capacitor, Etc.) Patents (Class 438/238)
  • Patent number: 10777456
    Abstract: Embodiments of systems and methods for semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process. In an embodiment, a method includes receiving a substrate with a patterned structure formed on a surface of the substrate. A method may also include depositing a first interconnect material in a first region of the patterned structure. Such methods may also include depositing a second interconnect material in a second region of the patterned structure, wherein the first interconnect material is different from the second interconnect material, and wherein the first region and the second region include a common layer of the patterned structures.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: September 15, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Hirokazu Aizawa, Kaoru Maekawa
  • Patent number: 10720577
    Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes conductive lines and a memory cell including a variable resistance element on one of the conductive lines. The variable resistance memory device includes a first insulating region between the conductive lines. Moreover, the variable resistance memory device includes a second insulating region on the first insulating region between the conductive lines. Methods of forming variable resistance memory devices are also provided.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Jae Kang, Gyuhwan Oh, Jiyoon Chung, Junyeon Hwang
  • Patent number: 10707271
    Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli
  • Patent number: 10632746
    Abstract: Methods and apparatuses for controlling aerosol streams being deposited onto a substrate via pneumatic shuttering. The aerosol stream is surrounded and focused by an annular co-flowing sheath gas in the print head of the apparatus. A boost gas flows to a vacuum pump during printing of the aerosol. A valve adds the boost gas to the sheath gas at the appropriate time, and a portion of the two gases is deflected in a direction opposite to the aerosol flow direction to at least partially prevent the aerosol from passing through the deposition nozzle. Some or all of the aerosol is combined with that portion of the boost gas and sheath gas and is exhausted from the print head. By precisely balancing the flows into and out of the print head, maintaining the flow rates of the aerosol and sheath gas approximately constant, and keeping the boost gas flowing during both printing and shuttering, the transition time between printing and partial or full shuttering of the aerosol stream is minimized.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 28, 2020
    Assignee: Optomec, Inc.
    Inventors: Kurt K. Christenson, Michael J. Renn, Jason A. Paulsen, John David Hamre, Chad Conroy, James Q. Feng
  • Patent number: 10608076
    Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: March 31, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10566334
    Abstract: Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Si-Woo Lee
  • Patent number: 10497788
    Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Youn Kim
  • Patent number: 10483462
    Abstract: Providing for improved manufacturing of silver-based electrodes to facilitate formation of a robust metallic filament for a resistive switching device is disclosed herein. By way of example, a silver electrode can be embedded with a non-silver material to reduce surface energy of silver atoms of a silver-based conductive filament, increasing structural strength of the conductive filament within a resistive switching medium. In other embodiments, an electrode formed of a base material can include silver material to provide mobile particles for an adjacent resistive switching material. The silver material can drift or diffuse into the resistive switching material to form a structurally robust conductive filament therein.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: November 19, 2019
    Assignee: Crossbar, Inc.
    Inventors: Sung Hyun Jo, Xianliang Liu, Fnu Atiquzzaman
  • Patent number: 10475829
    Abstract: A semiconductor apparatus includes a conductive member including a polycrystalline silicon layer having a first, second and third portions, an interlayer insulation film that covers the conductive member, a first silicon nitride layer arranged between the interlayer insulation film and the third portion, a second silicon nitride layer arranged between the interlayer insulation film and the first portion and between the interlayer insulation layer and the second portion, a first contact plug disposed above the first portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member, and a second contact plug disposed above the second portion and penetrating the interlayer insulation film and the second silicon nitride layer to connect to the conductive member. The first silicon nitride layer is disposed between the first and second contact plugs, and apart from the first and second contact plugs.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: November 12, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Mitsuhiro Yomori, Takehito Okabe, Nobuaki Kakinuma, Takashi Okagawa
  • Patent number: 10468478
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10446444
    Abstract: An interconnection structure of the semiconductor integrated circuit device may be provided. The interconnection structure may include a first conductive pattern, a second conductive pattern, a dielectric layer and a contact part. The first conductive pattern may have a first width and a first length. The second conductive pattern may be formed over the first conductive pattern. The second conductive pattern may have a second width and a second length. The dielectric layer may be interposed between the first conductive pattern and the second conductive pattern. The contact part may be configured to simultaneously make contact with the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Jong Su Kim
  • Patent number: 10437089
    Abstract: A display device includes a display panel, a support frame including a plurality of straight portions located at two adjacent outer side surfaces of the display panel and having a substantially equal cross-section and a curved portion connecting the plurality of straight portions and having a curvature, a plurality of protrusion frames each extending from a straight portion of the plurality of straight portions of the support frame toward an inner portion of the display panel, and a mold portion overlapping the plurality of protrusion frames to be joined with the plurality of protrusion frames and being located along an inner surface of the curved portion of the support frame.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minsu Jung, Youngnam Kim
  • Patent number: 10361092
    Abstract: A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant, with a coolant temperature below ?20° C. An etch gas comprising a metal containing component, a carbon containing component, and a halogen containing component is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched in the stack with respect to the patterned mask.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 23, 2019
    Assignee: Lam Research Corporation
    Inventors: Francis Sloan Roberts, Eric Hudson
  • Patent number: 10332986
    Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10269805
    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Chandra Mouli, Sanh D. Tang
  • Patent number: 10256318
    Abstract: A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: April 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-ho Jeon, Dae-hyun Jang, Seung-seok Ha, Young-ju Park, Sun-ki Min
  • Patent number: 10199472
    Abstract: A neuromorphic device includes a row line extending in a first direction; a column line disposed over the row line, the column line extending in a second direction perpendicular to the first direction; a plurality of gating lines disposed between the row line and the column line; and a synapse disposed between the row line and the column line, the synapse passing through the plurality of gating lines.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 5, 2019
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 10164181
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Hsueh Yang, Yuan-Tai Tseng, Yi-Jen Tsai, Shih-Chang Liu
  • Patent number: 10111207
    Abstract: The present invention relates to a network device, a terminal device, and a voice service control method, a frame type of voice data is determined, and therefore, a voice service of the network device may be disconnected when no speech frame time exceeds set time, which prevents an economic loss caused by a non-talking call maintained for a long time, thereby saving a resource of an operator network, and improving utilization efficiency of the operator network.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: October 23, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaoqiong Long, Qiang Yuan, Chunjie Yang
  • Patent number: 10086622
    Abstract: The object of the invention is the provision of apparatuses and methods for stable direct printing of continuous films or discreet structures on a substrate using an internal pneumatic shutter. The invention uses an aerodynamic focusing technique, with a print head comprising an aerosolization source, a flow cell, an aerodynamic lens system, and a pneumatic shutter assembly. The method uses an interchangeable and variable aerodynamic lens system mounted in the flow cell, and an annularly flowing sheath gas to produce a highly collimated micrometer-size stream of aerosolized droplets. The lens system is comprised of a single-orifice or multi-orifice lens coupled to a converging fluid dispense nozzle. A liquid atomizer with temperature control is used to produce an aerosol size distribution that overlaps the functional range of the aerodynamic lens system. The shutter assembly can be attached directly to the print head, or mounted external to the print head in a control module.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: October 2, 2018
    Assignee: Integrated Deposition Solutions, Inc.
    Inventors: Marcelino Essien, David Michael Keicher
  • Patent number: 10084053
    Abstract: Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A first metal gate electrode and a second metal gate electrode are formed that are embedded in a first dielectric layer. A second dielectric layer is formed on the first metal gate electrode, the second metal gate electrode, and the first dielectric layer. An opening is formed in the second dielectric layer that extends in a vertical direction to expose a section of the first metal gate electrode. The section of the first metal gate electrode is removed, while the second metal gate electrode is masked by the second dielectric layer, to define a gate cut at a location of the opening. The gate cut may be subsequently filled by dielectric material.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Min Gyu Sung
  • Patent number: 10062699
    Abstract: A capacitor for a semiconductor memory element includes a lower electrode, a dielectric layer disposed on the lower electrode and including titanium oxide, and an upper electrode disposed on the dielectric layer. The lower electrode includes a first metal and a second metal, the first metal including at least one selected from the group consisting of platinum (Pt), osmium (Os), rhodium (Rh) and palladium (Pd), the second metal including at least one selected from the group consisting of ruthenium (Ru) and iridium (Jr).
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: August 28, 2018
    Assignee: Korea Institute of Science and Technology
    Inventors: Seong Keun Kim, Jung Joon Pyeon, Cheol Jin Cho, Sangtae Kim, Doo Seok Jeong, Seung-Hyub Baek, Chong-Yun Kang, Ji-Won Choi, Jin-Sang Kim
  • Patent number: 9917250
    Abstract: A switching device includes a first electrode and a second electrode that are disposed over a substrate, and an electrolyte layer disposed between the first electrode and the second electrode and including a porous oxide. The switching device performs threshold switching operation on the basis of oxidation-reduction reactions of metal ions that are provided from the first electrode or the second electrode to the electrolyte layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: March 13, 2018
    Assignee: SK HYNIX INC.
    Inventors: Beom Yong Kim, Soo Gil Kim, Won Ki Ju
  • Patent number: 9755064
    Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm?3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm?3 or less.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Yuichiro Mitani, Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 9691780
    Abstract: The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
  • Patent number: 9679960
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 9627257
    Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 18, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Su Chen Fan, Andre P. Labonte, Lars W. Liebmann, Sanjay C. Mehta
  • Patent number: 9608204
    Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Hao Lee, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 9577030
    Abstract: Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: February 21, 2017
    Assignee: Intel Corporation
    Inventor: Nick Lindert
  • Patent number: 9553258
    Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 24, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 9508712
    Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jeremy Austin Wahl, Nicholas Vincent LiCausi
  • Patent number: 9496327
    Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Paul Campbell, Kaiping Liu
  • Patent number: 9490206
    Abstract: An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Gunther Lehmann, Franz Ungar
  • Patent number: 9478625
    Abstract: A semiconductor structure includes a semiconductor substrate, fins coupled to the substrate and surrounded at a bottom portion thereof by isolation material, and resistor(s) situated in the gate region(s), the gate regions being filled with undoped dummy gate material. As part of a replacement gate process, the resistor(s) are realized by forming silicide over dummy gate material, i.e., the dummy gate material for the resistor(s) is not removed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-hwa Chi, Huang Liu
  • Patent number: 9337020
    Abstract: A method for processing a resist mask includes: (a) a step of preparing, in a processing chamber, a target object to be processed having a patterned resist mask provided thereon; and (b) a step of generating a plasma of the hydrogen-containing gas by supplying a hydrogen-containing gas and supplying a microwave into the processing chamber. The hydrogen-containing gas may be, e.g., H2 gas.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 10, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Michihisa Takachi, Yusuke Shimizu, Toshihisa Ozu
  • Patent number: 9331083
    Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: May 3, 2016
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Serguei Okhonin, Viktor Koldiaev, Mikhail Nagoga, Yogesh Luthra
  • Patent number: 9331138
    Abstract: A semiconductor device includes a first storage electrode, a second storage electrode that is arranged above the first storage electrode, a first landing pad that is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode, the first landing pad connecting the first storage electrode and the second storage electrode, the first landing pad having a first landing surface, the first landing surface being larger than the bottom surface of the second storage electrode, and the second storage electrode being placed on the first landing surface, a capacitive insulating film that is laminated on the first and second storage electrodes and on an outer circumferential surface of the first landing pad, and a plate electrode that contacts the capacitive insulating film.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 3, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Takashi Miyajima
  • Patent number: 9324945
    Abstract: A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable material and the outer electrode material contact one another along an interface. Protective material is formed elevationally over the outer electrode material. Dopant is implanted through the protective material into the outer electrode material and the programmable material and across the interface to enhance adhesion of the outer electrode material and the programmable material relative one another across the interface. Memory cells are also disclosed.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Lequn Jennifer Liu, Stephen W. Russell, Fabio Pellizzer, Swapnil Lengade
  • Patent number: 9318604
    Abstract: A semiconductor device includes a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film, a plurality of junction regions including storage node junction regions and a bit line junction region disposed between the storage node junction regions, a plurality of storage node contact plugs respectively disposed over and coupled to the storage node junction regions, a plurality of storage nodes respectively disposed over and coupled to the storage node contact plugs, and a second gate electrode disposed over a sidewall of a corresponding one of the storage node contact plugs. A vertical transistor includes the second gate electrode and the corresponding storage node contact plug and stores charges leaked from a corresponding one of the storage nodes.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 19, 2016
    Assignee: SK HYNIX INC.
    Inventor: Il Woong Kwon
  • Patent number: 9293411
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: March 22, 2016
    Assignee: SONY CORPORATION
    Inventor: Masanaga Fukasawa
  • Patent number: 9293336
    Abstract: A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangryol Yang, Soonwook Jung, Kyoungseob Kim, Youngsub You, Byunghong Chung, Hanmei Choi
  • Patent number: 9287346
    Abstract: A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Yun Lee, Moo-Jin Kim
  • Patent number: 9263548
    Abstract: A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: February 16, 2016
    Inventor: Tzu-Yin Chiu
  • Patent number: 9252104
    Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: February 2, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: John J. Zhu, Bin Yang, Pr Chidambaram, Lixin Ge, Jihong Choi
  • Patent number: 9236427
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 9224738
    Abstract: A method of forming an array of gated devices includes forming trenches between walls that longitudinally extend in rows and project elevationally from a substrate. The walls comprise semiconductor material. Gate dielectric is formed within the trenches laterally over side surfaces of the walls and conductive gate material is formed within the trenches laterally over side surfaces of the gate dielectric. Side surfaces of an elevationally inner portion of the gate material within the trenches are laterally covered with masking material and side surfaces of an elevationally inner portion of the gate material within the trenches are laterally uncovered by the masking material. The elevationally outer portion of the gate material that is laterally uncovered by the masking material is removed while the side surfaces of the elevationally inner portion of the gate material are laterally covered by the masking material to form gate lines within the trenches laterally over elevationally inner portions of the walls.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: December 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Federica Zanderigo, Marcello Mariani, Alessandro Grossi
  • Patent number: 9224784
    Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a plurality of impurity regions formed in a substrate, a first contact electrically connected to at least one of the impurity regions, a second contact electrically connected to at least one of the impurity regions, a first information storage portion formed at a first height from the substrate and electrically connected to the first contact, and a second information storage portion formed at a second height, which is different from the first height, from the substrate and electrically connected to the second contact.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 29, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whan-Kyun Kim, Young-Hyun Kim, Woo-Jin Kim
  • Patent number: 9214572
    Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 15, 2015
    Assignee: MONOLITH SEMICONDUCTOR INC.
    Inventors: Sujit Banerjee, Kevin Matocha, Kiran Chatty
  • Patent number: 9147679
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, ltd.
    Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
  • Patent number: 9136469
    Abstract: A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: September 15, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Ying Li, Neil Zhu, Guanping Wu