Utilizing Stacked Capacitor Structure (e.g., Stacked Trench, Buried Stacked Capacitor, Etc.) Patents (Class 438/244)
  • Patent number: 10505109
    Abstract: A resistive random access memory (Device) is disclosed. The Device includes a substrate, a first electrode formed atop the substrate, a tunneling barrier layer formed atop the first electrode, an active material formed atop the tunneling barrier layer, an isolation layer formed atop the active material, and a second electrode formed atop the isolation layer, the first electrode and the second electrode provide electrical connectivity to external components, where the active material is a phase change material which undergoes phase transition in the presence of an electric field, Joule heating, or a combination thereof.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: December 10, 2019
    Assignee: Purdue Research Foundation
    Inventors: Joerg Appenzeller, Feng Zhang, Yuqi Zhu
  • Patent number: 9018060
    Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 28, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Stefan H. Gryska, Michael C. Palazzotto
  • Patent number: 9006061
    Abstract: A method of forming a capacitor comprises forming a first electrode of the capacitor over a substrate. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures on the bottom conductive plane. The method also comprises forming an insulating structure over the first electrode. The method further comprises forming a second electrode of the capacitor over the insulating structure. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures under the top conductive plane. The first vertical conductive structures of the plurality of first vertical conductive structures and the second vertical conductive structures of the plurality of second vertical conductive structures are interlaced with each other.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chen Ho-Hsiang, Fred Kuo, Tse-Hul Lu
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8994144
    Abstract: A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jae-Soo Kim, Hyung-Kyun Kim
  • Patent number: 8975133
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Patent number: 8932933
    Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ian C. Laboriante, Prashant Raghu
  • Patent number: 8860113
    Abstract: A semiconductor structure is disclosed in which, in an embodiment, a first substrate includes at least one buried plate disposed in an upper part of the first substrate. Each of the at least one buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, John E. Barth, John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8853033
    Abstract: A method for fabricating a semiconductor device includes: sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n? type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n? type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide fi
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Kyoung-Kook Hong, Jong Seok Lee, Dae Hwan Chun
  • Patent number: 8853048
    Abstract: The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process. A hard mask is formed over the substrate and etched through the mask to form two or more closely spaced trenches. The hard mask is then reduced by an isotropic etch process. The etch removes the hard mask preferentially between the trenches. Chemical mechanical polishing removes the conductive material down to the remaining hard mask layer, whereby conductive material remains in mask openings and forms a conductive bridge across the trenches.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wu-An Weng, Chen-Chien Chang
  • Patent number: 8835250
    Abstract: A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jonathan E. Faltermeier, Veeraraghavan S. Basker, Kangguo Cheng, Theodorus Eduardus Standaert
  • Patent number: 8835330
    Abstract: A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Chen, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8815679
    Abstract: First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang
  • Patent number: 8815677
    Abstract: A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Wim Deweerd, Xiangxin Rui, Sandra Malhotra, Hiroyuki Ode
  • Patent number: 8815695
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Mitsuhiro Horikawa, Hiroyuki Ode, Karthik Ramani
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: 8779491
    Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Fen Chen, Baozhen Li
  • Patent number: 8765535
    Abstract: In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 8766232
    Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukhun Choi, Boun Yoon, Kevin Ahn, Doo-Sung Yun
  • Patent number: 8766410
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 8748258
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam Shahidi
  • Patent number: 8709890
    Abstract: An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8710567
    Abstract: The semiconductor device of the present invention includes a silicon substrate having a logic region and a RAM region, an NMOS transistor formed in the logic region, and an NMOS transistor formed in the RAM region. The NMOS transistor has a stack structure obtained by sequentially stacking the gate insulating film and the metal gate electrode over the silicon substrate. The NMOS transistor has a cap film containing an element selected from a group consisting of lanthanum, ytterbium, magnesium, strontium, and erbium as a composition element between the silicon substrate and metal gate electrode. The cap film is not formed in the NMOS transistor.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiko Moriya
  • Patent number: 8698322
    Abstract: A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 15, 2014
    Assignee: Oracle International Corporation
    Inventors: Robert J. Drost, Ashok V. Krishnamoorthy, John E. Cunningham
  • Patent number: 8697534
    Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 15, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Motohiko Sato, Kazuhiro Hayashi, Kenji Murakami, Motonobu Kurahashi, Yusuke Kaieda, Jun Otsuka, Manabu Sato
  • Patent number: 8691656
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Patent number: 8680599
    Abstract: To provide a more reliable semiconductor device including a lower-cost and more reliable capacitor and a method of manufacturing the same. This manufacturing method comprises the steps of: preparing a semiconductor substrate; and forming, over one of the major surfaces of the semiconductor substrate, a first metal electrode including an aluminum layer, a dielectric layer over the first metal electrode, and a second metal electrode over the dielectric layer. In the step of forming the first metal electrode, the aluminum layer is formed so that the surface thereof satisfies a relationship of Rmax<80 nm, Rms<10 nm, and Ra<9 nm. The step of forming the first metal electrode comprises the steps of: forming at least one first barrier layer; forming the aluminum layer over the first barrier layer; and recrystallizing a crystal constituting the aluminum layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Mitsuyama, Yasuhisa Fujii, Keiichi Yamada
  • Patent number: 8673719
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8658494
    Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: February 25, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Juergen Boemmels, Matthias Schaller, Sven Mueller
  • Patent number: 8652920
    Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: February 18, 2014
    Assignee: Kamet Electronics Corporation
    Inventors: John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn
  • Patent number: 8633036
    Abstract: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8623725
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 8617949
    Abstract: A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
  • Patent number: 8592979
    Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee
  • Patent number: 8586444
    Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jennifer E. Appleyard, John E. Barth, Jr., John B. DeForge, Herbert L. Ho, Babar A. Khan, Kirk D. Peterson, Andrew A. Turner
  • Patent number: 8587047
    Abstract: A capacitor structure for a pumping circuit includes a substrate, a U-shaped bottom electrode in the substrate, a T-shaped top electrode in the substrate and a dielectric layer disposed between the U-shaped bottom and T-shaped top electrode. The contact area of the capacitor structure between the U-shaped bottom and T-shaped top electrode is extended by means of the cubic engagement of the U-shaped bottom electrode and the T-shaped top electrode.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: November 19, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Wei Ting, Shing-Hwa Renn, Yu-Teh Chiang, Chung-Ren Li, Tieh-Chiang Wu
  • Patent number: 8530312
    Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Filippini, Luca Ferrario, Marcello Mariani
  • Patent number: 8530330
    Abstract: A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: September 10, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sang Tae Ahn, Ja Chun Ku, Eun Jeong Kim, Wan Soo Kim
  • Patent number: 8492819
    Abstract: A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, John E. Barth, Jr., Edward J. Nowak, Jed H. Rankin
  • Patent number: 8492816
    Abstract: Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: James S. Nakos, Edmund J. Sprogis, Anthony K. Stamper
  • Patent number: 8486800
    Abstract: A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: July 16, 2013
    Assignee: NXP B.V.
    Inventors: Jin Liu, Aarnoud Laurens Roest, Freddy Roozeboom, Vahid Shabro
  • Patent number: 8486784
    Abstract: A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: July 16, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Jung Kim
  • Patent number: 8470680
    Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: June 25, 2013
    Assignees: Kemet Electronics Corporation, Motorola, Inc.
    Inventors: John D. Prymak, Chris Stolarski, Alethia Melody, Antony P. Chacko, Gregory J. Dunn
  • Patent number: 8470668
    Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: June 25, 2013
    Assignee: SK Hynix Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Dong Kyun Lee
  • Patent number: 8455360
    Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 4, 2013
    Assignee: SK Hynix Inc.
    Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
  • Patent number: 8445367
    Abstract: In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Tae Noh, Hun-Hyeong Lim, Ki-Hyun Hwang, Jin-Gyun Kim, Sang-Ryol Yang
  • Patent number: 8431981
    Abstract: A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: April 30, 2013
    Assignee: SK Hynix Inc.
    Inventors: Baek Mann Kim, Jun Ki Kim, Yong Seok Eun, Kyong Bong Rouh
  • Patent number: 8410536
    Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: April 2, 2013
    Assignee: Kemet Electronics Corporation
    Inventors: John D. Prymak, Chris Stolarski, Alethia Melody, Antony P. Chacko, Gregory J. Dunn
  • Patent number: RE46204
    Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Miwako Akiyama, Yoshihiro Yamaguchi, Nobuyuki Sato, Shigeaki Hayase