Trench Capacitor Patents (Class 438/243)
  • Patent number: 10431491
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a semiconductor layer having a first conductivity type on a semiconductor substrate, forming a trench in the semiconductor substrate and the semiconductor layer, forming a semiconductor film having a second conductivity type on an inner wall surface and a bottom surface of the trench, forming a first insulating film including silicon oxide on a side surface and a bottom surface of the semiconductor film, forming a second insulating film including silicon nitride on a side surface and a bottom surface of the first insulating film, and forming a third insulating film including silicon oxide on a side surface and a bottom surface of the second insulating film.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 1, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yuhki Fujino, Noboru Yokoyama, Hideki Okumura
  • Patent number: 10418366
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Patent number: 10410854
    Abstract: The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Honghui Mou, Xiaodong Li, Yun Ling Tan, Alex See, Liang Li
  • Patent number: 10396195
    Abstract: A semiconductor device is provided and includes an n? type layer disposed at a substrate first surface. A trench, n type region, and p+ type region are disposed on the n? type layer. A p type region is disposed on the n type region. An n+ type region is disposed on the p type region. A gate insulating layer is disposed in the trench. A gate electrode is disposed on the gate insulating layer. A source electrode is disposed on an insulating layer disposed on the gate electrode, n+ type region, and p+ type region. A drain electrode is disposed at a substrate second surface. The n type region includes a first portion contacting the trench side surface and extending parallel to a substrate upper surface and a second portion contacting the first portion, separated from the trench side surface, and extending vertical to the substrate upper surface.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 27, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 10396073
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 27, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Chien-Ting Ho, Shih-Fang Tzou
  • Patent number: 10381475
    Abstract: A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Andreas Meiser, Karl-Heinz Gebhardt, Till Schloesser, Detlef Weber
  • Patent number: 10236382
    Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10198677
    Abstract: An RFID tag is disclosed that is formed as part of a printed fabric label (PFL). Generally, foil is adhered to a fabric material with a releasable adhesive, the foil is then cut, such as by a laser to define the antenna pattern and a removable portion. The removable portion is then manually stripped away, and a strap is then attached with adhesive to the antenna. A small square of hot melt over-laminate may be placed over the strap and bonded, and then a top layer of fabric is added and secured with an adhesive from a transfer tape.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 5, 2019
    Assignee: AVERY DENNISON RETAIL INFORMATION SERVICES, LLC
    Inventor: Ian J. Forster
  • Patent number: 9881904
    Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: January 30, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Mark A. Gouker, Pascale Gouker, Leonard M. Johnson, Ryan C. Johnson
  • Patent number: 9722043
    Abstract: A method of forming a finFET device includes forming a plurality of fins on a substrate; forming a plurality of dummy gate structures over the plurality of fins, the dummy gate structures including gate sidewall spacers; performing an epitaxial growth process to merge the plurality of fins at locations not covered by the dummy gate structures; forming an interlevel dielectric (ILD) layer over the dummy gate structures and merged fins, the ILD layer comprising a first dielectric material; removing portions of the ILD layer and the merged fins so as to define trenches; and filling the trenches with a second dielectric material having an etch selectivity with respect to the first dielectric material, and wherein the gate sidewall spacers also comprise the second dielectric material such that regions of the merged fins in active areas are surrounded by the second dielectric material.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng
  • Patent number: 9659930
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Yu, Sheng-chen Wang, Sai-Hooi Yeong
  • Patent number: 9595521
    Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yen Chou, Po-Ken Lin, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 9553018
    Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker
  • Patent number: 9530884
    Abstract: A method of manufacturing a semiconductor device including a transistor comprises forming field plate trenches in a main surface of a semiconductor substrate, a drift zone being defined between adjacent field plate trenches, forming a field dielectric layer in the field plate trenches, thereafter, forming gate trenches in the main surface of the semiconductor substrate, a channel region being defined between adjacent gate trenches, and forming a conductive material in at least some of the field plate trenches and in at least some of the gate trenches. The method further comprising forming a source region and forming a drain region in the main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 9412655
    Abstract: A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a hard mask layer formed above the first dielectric layer. Portions of the first dielectric layer exposed by the line merge opening are removed to define a line merge recess. A portion of a selected sacrificial line exposed by the line cut opening is removed to define a line cut recess between first and second segments of the selected sacrificial line. A second dielectric layer is formed in the line cut recess. The hard mask is removed. The plurality of sacrificial lines is replaced with a conductive material to define at least one line having third and fourth segments in locations previously occupied by the first and second segments and to define a line-merging conductive structure in the line merge recess.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: August 9, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guillaume Bouche, Jason E. Stephens, Vikrant Chauhan, Andy C. Wei
  • Patent number: 9397152
    Abstract: A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 9368356
    Abstract: Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: June 14, 2016
    Assignee: SK hynix Inc.
    Inventor: Jung-Nam Kim
  • Patent number: 9337283
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, a first electrode which extends in a first direction and is surrounded by the first semiconductor layer except at one end thereof, and a first insulation film which is formed between the first semiconductor layer and the first electrode. A film thickness of the first insulation film between the other end of the first electrode in a second direction opposite to the first direction and the first semiconductor layer includes a thickness that is greater than a thickness of the first insulation film along a side surface of the first electrode. The semiconductor device also includes a second electrode which faces the second semiconductor layer, and a second insulation film which is formed between the second electrode and the second semiconductor layer.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshifumi Nishiguchi
  • Patent number: 9299766
    Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Nicolas L. Breil, Ricardo A. Donaton, Dong Hun Kang, Herbert L. Ho, Rishikesh Krishnan
  • Patent number: 9299793
    Abstract: Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: March 29, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Timothy D. Henson, Kapil Kelkar, Ljubo Radic
  • Patent number: 9293376
    Abstract: A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Chun-Wai Ng, Ruey-Hsin Liu
  • Patent number: 9257497
    Abstract: Some embodiments relate to a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a capacitor bottom metal (CBM) electrode, a high-k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. A capping layer is arranged over the CTM electrode. A lower surface of the capping layer and an upper surface of the CTM electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the CTM electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the CTM electrode meets the lower surface of the capping layer.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Patent number: 9224797
    Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John E. Barth, Jr., Herbert L. Ho, Babar A. Khan, Kirk D. Peterson
  • Patent number: 9214378
    Abstract: A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9190410
    Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang
  • Patent number: 9159710
    Abstract: A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine. The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated, its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.).
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: October 13, 2015
    Assignee: CORNELL UNIVERSITY
    Inventors: Amit Lal, Kwame Amponsah
  • Patent number: 9134910
    Abstract: A request is output to a first queue of a storage device. A head flag of the request is set based on whether the request is a read type request and a comparison of a percentage of requests queued at the first queue that are read type requests to a threshold percentage. The storage device is to store the request at a head of the first queue if the head flag of the request is set.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 15, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark J. Thompson, Timothy W J Majni
  • Patent number: 9087928
    Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Kangguo Cheng, Joseph Ervin, David M. Fried, Byeong Y. Kim, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 9076680
    Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
  • Patent number: 9059290
    Abstract: A method includes patterning a fin on a semiconductor substrate, depositing a local trench isolation (LTI) layer on the semiconductor substrate, patterning a gate stack over a channel region of the fin and over a portion of the LTI layer, depositing a first capping layer over exposed portions of the LTI layer, performing an etching process to remove oxide material from exposed portions of the fin, and epitaxially growing a semiconductor material from exposed portions of the fin to define active regions.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai, Reinaldo A. Vega
  • Patent number: 9053956
    Abstract: A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Xi Li, Geng Wang
  • Patent number: 9048130
    Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Publication number: 20150145010
    Abstract: After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: International Business Corporation
    Inventors: Herbert L. Ho, Ravikumar Ramachandran, Reinaldo A. Vega
  • Patent number: 9023695
    Abstract: The present disclosure provides a method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chao Chiu, Nian-Fuh Cheng, Chen-Yu Chen, Ming-Feng Shieh, Chih-Ming Lai, Wen-Chun Huang, Ru-Gun Lin
  • Patent number: 9018052
    Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8999821
    Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Adam Brand, Bingxi Wood, Errol Sanchez, Yihwan Kim, Yi-Chiau Huang, John Boland
  • Patent number: 9000494
    Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Fei Liu, Ying Zhang
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8980714
    Abstract: A method of manufacturing a semiconductor device includes introducing at least a first and a second trench pattern from a first surface into a semiconductor substrate. An array isolation region including a portion of the semiconductor substrate separates the first and second trench patterns. At least the first trench pattern includes array trenches and a contact trench which is structurally connected with the array trenches. A buried gate electrode structure is provided in a lower section of the first and second trench patterns in a distance to the first surface. A connection plug is provided between the first surface and the gate electrode structure in the contact trench. Gate electrodes of semiconductor switching devices integrated in the same semiconductor portion can be reliably separated and internal gate electrodes can be effectively connected in a cost-effective manner.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marko Lemke, Rolf Weis, Stefan Tegen
  • Patent number: 8975133
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Publication number: 20150060972
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: November 5, 2014
    Publication date: March 5, 2015
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8963287
    Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Lei Tian, Scott W. Barry, Xuejun Ying
  • Patent number: 8962423
    Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8956961
    Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Rexchip Electronics Corporation
    Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
  • Publication number: 20150037947
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Felix Beaudoin, Stephen M. Lucarini, Xinhui Wang, Xinlin Wang
  • Patent number: 8946908
    Abstract: Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8941210
    Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Tai Ho Kim
  • Patent number: 8936992
    Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Patent number: 8932932
    Abstract: An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Anne Marie Kimball