Abstract: A CMOS device is disclosed, including a plurality of active regions having a length along a first direction, wherein the active regions are arranged end-to-end along the first direction and are separated by an isolation structure. A recessed region is formed in the isolation structure between the adjacent terminals of the each pair of neighboring active regions and is completely filled by an interlayer dielectric layer, wherein the interlayer dielectric layer comprises a stress.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.

Abstract: Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value.

Abstract: A semiconductor device includes a substrate, a conductive pattern (e.g., a contact plug) on an active region of the substrate and having respective first and second sidewalls on opposite first and second sides of the conductive pattern, and first and second conductive lines (e.g., bit lines) on the substrate on respective ones of the first and second sides of conductive pattern and separated from the respective first and second sidewalls by asymmetric first and second air spaces.

Abstract: An exemplary method for fabricating a metal gate electrode includes providing a substrate having thereon a dielectric layer and a trench in the dielectric layer; depositing a work-function metal layer over the dielectric layer and into the trench; depositing a sacrificial layer over the work-function metal layer to fill the first trench; performing a chemical mechanical polishing to remove the work-function metal layer outside the trench; removing the sacrificial layer in the trench; and depositing a signal metal layer to fill the trench.

Abstract: Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization.

Abstract: An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed.

Abstract: Methods of selectively forming a conductive material and methods of forming metal conductive structures are disclosed. An organic material may be patterned to expose regions of an underlying material. The underlying material may be exposed to a precursor gas, such as a platinum precursor gas, that reacts with the underlying material without reacting with the remaining portions of the organic material located over the underlying material. The precursor gas may be used in an atomic layer deposition process, during which the precursor gas may selectively react with the underlying material to form a conductive structure, but not react with the organic material. The conductive structures may be used, for example, as a mask for patterning during various stages of semiconductor device fabrication.

Abstract: The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.

Abstract: An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening (51t) where a portion of a top electrode is exposed and an opening (51b) where a portion of a bottom electrode is exposed are formed in the aluminum oxide film. Thereafter, films (23 to 26) are formed and a resist pattern (92) is formed. Then, etching of the films (23 to 26) is performed with using the resist pattern (92) as a mask thereby forming contact holes (27t) and (27b). At this time, since the openings (51t) and (51b) are formed in the aluminum oxide film, the aluminum oxide film is not required to be processed. Consequently, the contact holes (27t) and (27b) can be formed easily.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.

Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.

Abstract: A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.

Abstract: An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.

Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.

Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film.

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.

Abstract: A method for forming a semiconductor device includes: etching a hard mask layer and a conductive layer formed on a semiconductor substrate, a lower structure being formed on the semiconductor substrate; forming a sacrificial insulating layer at upper parts of the etched hard mask layer and the etched conductive layer of a peripheral circuit region; forming an isolation insulating layer at an upper part of an isolation insulating layer of a cell region; forming spacers at sidewalls of the etched hard mask layer, the etched conductive layer, and the isolation insulating layer of the cell region, respectively; forming storage electrode contact plugs at both sides of each of the spacers, respectively; and removing the sacrificial insulating layer to expose the semiconductor substrate of the peripheral circuit region, and etching the lower structure to expose the semiconductor substrate of the peripheral circuit region.

Abstract: It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized.

Abstract: A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from the semiconductor material; at least one recess in the gate electrode, a through-contact arranged in the recess of the gate electrode, the through-contact being electrically insulated from the gate electrode; a terminal contact on the semiconductor material; and a terminal conductor arranged on the side of the gate electrode that faces away from the substrate, wherein the through-contact electrically connects the terminal contact to the terminal conductor.

Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.

Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.

Abstract: Fabrication methods for electronic devices with via through holes and thin film transistor devices are presented. The fabrication method the electronic device includes providing a substrate, forming a patterned lower electrode on the substrate, and forming a photosensitive insulating layer on the substrate covering the patterned lower electrode. A patterned optical shielding layer is applied on the photosensitive insulating layer. Exposure procedure is performed curing the exposed photosensitive insulating layer. The optical shielding layer and the underlying photosensitive insulating layer are sequentially removed, thereby forming an opening. A patterned upper electrode is formed on the photosensitive insulating layer filling the opening to create a conductive via hole.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.

Abstract: Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.

Abstract: Provided is a method of fabricating a semiconductor device having a transistor. The method includes forming a first gate trench in a first active region of a semiconductor substrate. A first gate layer partially filling the first gate trench is formed. Ions may be implanted in the first gate layer and in the first active region on both sides of the first gate layer such that the first gate layer becomes a first gate electrode of a first conductivity type and first impurity regions of the first conductivity type are formed on both sides of the first gate electrode.

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flattened shape generally parallel to a plane of the resin layer.

Abstract: A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.

Abstract: Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout.

Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.

Abstract: A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area.

Abstract: Embodiments of the invention relate to a silicon semiconductor device, and a conductive thick film composition for use in a solar cell device.

Abstract: A method for fabricating a storage node electrode in a semiconductor device includes: performing a primary high density plasma (HDP) process to form a first HDP oxide film over an etch stop film; performing a secondary HDP process to form a second HDP oxide film on the first HDP oxide film; forming a support film over the second HDP oxide film; performing a tertiary HDP process to form a third HDP oxide film over the support film; forming a storage node electrode on an exposed surface of the storage node contact hole; partially removing the third HDP oxide film and the support film so that a support pattern supporting the storage node electrode is formed; and exposing an outer surface of the storage node electrode by removing the second HDP oxide film and the first HDP oxide film.

Abstract: A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.

Abstract: The disclosure provides a method of forming a ferromagnetic material, including: forming a magnetic element layer on a semiconductor layer formed on an inhibition layer; and forming a ferromagnetic layer of a Heusler alloy layer on the inhibition layer by heat treatment to induce the semiconductor layer and the magnetic element layer to react with each other, and a transistor, and a method of manufacturing the same. The inhibition layer for inhibiting a reaction of the semiconductor layer and the magnetic element layer restricts a semiconductor to be supplied for a reaction of the semiconductor and the magnetic element. Therefore, it is possible to form a ferromagnetic material having a high composition ratio of a magnetic element.