Abstract: A nonvolatile memory includes a semiconductor substrate having a body member and a step member formed on the body member, a highly doped first well layer formed on the step member, a control electrode formed on the step member, a first and a second diffusion layers in the substrate, lightly doped second well layers formed on the main surface of the substrate between the first or the second diffusion layer and the first well layer, and a first and a second charge-storage multi-layers sandwiching the step member and the control electrode, each of the first and the second charge-storage multi-layers including a bottom oxide layer, a charge-storage film, a top oxide layer and a floating electrode which are formed in that order.

Abstract: Provided is a method for manufacturing a flash memory device that can improve uniformity. In one method, an oxide chemical mechanical polishing process is performed to remove a height difference of the interlayer insulating layer that is generated between the cell area and the peripheral area due to the gate stack formed in the cell area that is not formed in the peripheral area.

Abstract: A method of fabricating a semiconductor device is provided. Spacers can be formed on adjacent gate structures and used as an ion implantation mask for forming source/drain regions. The spacers can include a nitride layer and an oxide layer. An etch stop layer can be provided between the gate structures, and the oxide layer can be removed from the spacers. A first oxide layer formed below the nitride layer can be protected from being etched away during removal of the oxide layer from the spacers by the etch stop layer. The etch stop layer and the first oxide layer can be removed, and an interlayer dielectric layer can be deposited.

Abstract: A flash memory device and a method of manufacturing a flash memory device are provided. The flash memory device includes a gate region on a semiconductor substrate, spacers on sidewalls of the gate region, and a passivation layer between the semiconductor substrate and a portion of each spacer.

Abstract: The present invention relates to a method for fabricating flash memory devices. The method may include the steps of forming an oxide/nitride/oxide (ONO) layer over a semiconductor substrate and a gate electrode on the ONO layer. Next, source/drain impurity region may be formed in a surface of the semiconductor substrate on both sides of the gate electrode and a pre-metal dielectric (PMD) layer may be formed over an entire surface of the semiconductor substrate including the gate electrode. Finally, a densification process for densifying the PMD layer may be performed under a gas atmosphere. A densification gas atmosphere used for densifying the PMD layer may include an H2 or N2/H2 atmosphere.

Abstract: A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell.

Abstract: A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

Abstract: Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

Abstract: A method of fabricating a flash memory includes forming a first oxide film over a semiconductor substrate, forming a metal film over the first oxide film, forming a photoresist pattern on the metal film, etching the metal film using the photoresist pattern as a mask and forming a metal film pattern, forming a second oxide film including the metal film pattern, and heat-treating the first and second oxide films at high temperature and processing the metal film pattern using metal oxide crystallization.

Abstract: A flash memory device fabricating method can include forming a plurality of gate patterns over a semiconductor substrate, forming a first spacer over the semiconductor substrate and against sidewalls of each gate pattern and a second spacer over the first spacer, forming an impurity region in the semiconductor substrate and between respective gate patterns, removing the second spacer, and then forming a pre-metal dielectric film over the semiconductor substrate including the gate patterns and the first spacer. The second space can be removed in order to expand a space between the gate patterns to thereby prevent generation of voids between the gate patterns.

Abstract: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate. The first memory cell includes a first control gate disposed on the substrate and a composite layer disposed between the first control gate and the substrate. The second memory cell includes a pair of floating gates disposed on the substrate, a second control gate disposed on the upper surface of the two floating gates, an inter-gate dielectric layer disposed between the floating gate and the second control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a gate dielectric layer disposed between the bottom of the second control gate and the substrate.

Abstract: A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

Abstract: A flash memory device having a spacer of a gate region formed in an oxide-nitride-oxide (ONO) structure and a source/drain region formed using the ONO structure. The outermost oxide in the ONO structure is removed and an interlayer insulating film is formed to ensure sufficient space between the gate regions. Thus, it is possible to prevent a void from being generated in the interlayer insulating film and prevent a word line from being electrically connected to a drain contact for forming a bit line.

Abstract: A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.

Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.

Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: A flash memory cell and a method for manufacturing the same are provided. The flash memory cell includes a tunnel oxide layer pattern, a floating gate on the tunnel oxide layer pattern, a first nitride layer pattern on the floating gate, an oxide-nitride-oxide (ONO) layer pattern on the first nitride layer pattern, and a control gate on the oxide-nitride-oxide layer pattern.

Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A method of manufacturing flash memory devices includes depositing a nitride film over a semiconductor substrate and forming an oxide film below the nitride film using an oxidization process involving an anneal process. A tunnel oxide film or an ONO2 oxide film having a thin thickness and a good film quality is formed and the operating performance of memory cells is improved.

Abstract: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

Abstract: An array of NROM flash memory cells configured to store at least two bits per four F2. Split vertical channels are generated along each side of adjacent pillars. A single control gate is formed over the pillars and in the trench between the pillars. The split channels can be connected by an n+ region at the bottom of the trench or the channel wrapping around the trench bottom. Each gate insulator is capable of storing a charge that is adequately separated from the other charge storage area due to the increased channel length.

Abstract: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Abstract: A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al2O3 and a polysilicon or SiO2 layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl3, Ar, and CH4 or He. The gas mixture further contains Cl2. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO2 layer are separately etched in different chambers.

Abstract: An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

Abstract: A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate.

Abstract: A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.

Abstract: Disclosed herein is a method of fabricating a flash memory device. The method includes providing a semiconductor substrate that includes an active region and a field region. A tunnel insulating layer and a first conductive layer are formed in the active region, and an isolation structure is formed in the field region. The method includes forming a dielectric layer along a surface of the first conductive layer and the isolation structure, forming a capping layer along a surface of the dielectric layer, and forming a hard mask layer over the capping layer. The method also includes performing a first etchant process to etch the capping layer and the dielectric layer over the isolation structure forming holes. The method further includes performing a second etch process to remove the hard mask layer to form an undercut in the dielectric layer. Still further, the method includes forming a second conductive layer over a structure in which the holes and the undercut are formed.

Abstract: A method for manufacturing a flash memory device includes: forming a floating gate on a tunnel oxide film formed on a semiconductor substrate; forming an ONO film on the floating gate; performing a well implant process to form a well on the semiconductor substrate; and performing an ashing process and a cleaning process using at least two of H2SO4, H2O2, HF, H2O, and O3. As a result, roughness is not generated on the upper surface of the ONO film which tends to cause data retention failures of the flash memory device during a high temperature operating life (HTOL) testing process, making it possible to improve the reliability of the flash memory device.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A method for manufacturing a semiconductor device includes: forming a first film on a base body; crystallizing the first film by heating; thinning the crystallized first film; and forming a second film on the thinned first film. The first film is made of a material having a high dielectric constant than silicon oxide. A semiconductor device includes: a silicon substrate; a tunnel insulating film provided on the silicon substrate; a floating gate electrode provided on the tunnel insulating film; a polycrystalline insulating film provided on the floating gate electrode; and a control gate electrode provided on the polycrystalline insulating film.

Abstract: Disclosed is a flash memory device comprising a semiconductor substrate in which a channel region is formed, an ONO (oxide-nitride-oxide) layer on the semiconductor substrate, a floating gate on the ONO layer, an anti-reflection layer on the floating gate; and a control gate on the anti-reflection layer. The channel region can be ion implanted before forming the floating gate.

Abstract: A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.

Abstract: Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

Abstract: A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.

Abstract: A nonvolatile memory device is formed by forming a first oxide layer on a substrate. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. The second oxide layer is patterned so as to expose the nitride layer. A first polysilicon layer is formed on the second oxide layer and the exposed portion of the nitride layer. The first polysilicon layer and the nitride layer are etched so as to expose the second oxide layer and the first oxide layer and to form polysilicon spacers on the nitride layer. The polysilicon spacers are etched so as to expose portions of the nitride layer. The exposed portions of the nitride layer may function as charge trapping layers. The exposed portion of the first oxide layer is etched to expose a portion of the substrate. A third oxide layer is formed on the exposed portion of the substrate, the exposed portions of the nitride layer, and the second oxide layer. A second polysilicon layer is formed on the third oxide layer.

Abstract: Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation film; forming a first insulation film covering the gate electrode and at least a part of the semiconductor substrate; charging the first insulation film; and forming a second insulation film for charge storage on the first insulation film.

Abstract: Embodiments relate to a three-dimensional flash memory cell and method of forming the same that may be improve the uniformity of flash memory cell by removing a width difference of a polysilicon pattern when forming a floating gate of flash memory device, to thereby improve the reliability of semiconductor device. The process may be simplified due to the self-alignment in the step of forming the polysilicon pattern, which may improve the yield.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A fabrication method for a non-volatile memory is provided. To fabricate the non-volatile memory, a plurality of first trenches and second trenches are formed in a substrate, wherein the second trenches are disposed above the first trenches and cross over the first trenches. Then, a tunneling layer and a charge storage layer are sequentially formed on both sidewalls of each second trench. An isolation layer is filled into the first trench. Furthermore, a charge barrier layer is formed on the sidewall of the second trench, and a gate dielectric layer is formed at the bottom of the second trench. A control gate layer is filled into the second trench. Finally, two first doping regions are formed in the substrate at both sides of the control gate layer.

Abstract: A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

Abstract: An insulating film provided below a floating gate electrode includes a first insulating film located at both end portions below the floating gate electrode, and a second insulating film sandwiched between the first insulating films and located in a middle portion below the floating gate electrode. The first insulating film and the second insulating film are formed in separate steps, and the first insulating film is thicker than the second insulating film. With this structure, when an insulating film is provided between the floating gate electrode and a silicon substrate to have a thickness more increased at its end portion than at its middle portion, the thickness can be increased more freely and a degree of the increase can be controlled more readily.

Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.

Abstract: A flash memory device includes control gates that are formed to completely surround the top and sides of floating gates. The control gates are located between the floating gates that are adjacent in the word line direction as well as the floating gates that are adjacent in the bit line direction. The present flash memory device reduces a shift in a threshold voltage resulting from interference among floating gates and increases an overlapping area of the floating gate and the control gates. Thus, there is an effect in that the coupling ratio can be increased.

Abstract: A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.

Abstract: A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.

Abstract: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height.

Abstract: A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element formation regions through a first gate insulation film, a control gate provided on the floating gate through a second gate insulation film, and source/drain regions provided in the semiconductor substrate, wherein a mutual diffusion layer is provided at least at an interface between the second gate insulation film and the control gate.

Abstract: A nonvolatile semiconductor memory device includes a first dielectric layer formed on the major surface of a semiconductor substrate, a floating gate electrode layer formed on the first dielectric layer, a second dielectric layer obtained by sequentially forming, on the floating gate electrode layer, a lower dielectric film mainly containing silicon and nitrogen, an intermediate dielectric film, and an upper dielectric film mainly containing silicon and nitrogen, a control gate electrode layer formed on the second dielectric layer, and a buried dielectric layer formed by covering the two side surfaces in the gate width direction of the stacked structure including the above-mentioned layers. The nonvolatile semiconductor memory device further includes a silicon oxide film formed near the buried dielectric layer in the interface between the floating gate electrode layer and lower dielectric film.