Abstract: A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow.

Abstract: A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes.

Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

Abstract: A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

Abstract: A semiconductor memory device includes a first insulation film, Charge accumulation portions, a second insulation film, and a control gate. The first insulation film is located on an active area (AA). The charge accumulation portions comprise minute crystals arranged on the first insulation film. A density of the charge accumulation portions at an end portion in an AA width direction of the first insulation film is higher than a density of the charge accumulation portions at a central potion in the AA width direction. The second insulation film is located on the first insulation film so as to coat the charge accumulation portions. The control gate is located on the second insulation film.

Abstract: Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a trapping material, forming two or more sub-layers of dielectric material on the trapping material, wherein a conduction band offset of each sub-layer of dielectric material is less than the conduction band offset of the material upon which it is formed, and forming a channel region on the two or more sub-layers of dielectric material. Methods of operating a back-side trap non-volatile memory cell include programming the memory cell via direct tunneling of carriers through an asymmetric band-gap tunnel insulator layer having two or more sub-layers formed beneath a channel region and having layers of material of increasing conduction band offset, and trapping the carriers in a trapping layer formed under the tunnel insulator layer.

Abstract: Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.

Abstract: Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction.

Abstract: A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device is disclosed. The semiconductor device includes a bit line formed to extend into a semiconductor substrate, a charge storage layer formed on the semiconductor substrate, a word line formed above the charge storage layer to extend across the bit line, a gate electrode formed on the charge storage layer under the word line and between bit lines, a first insulating film formed over the bit line and to extend in the direction of the bit line and a second insulating film that includes a different material than that of the first insulating film and formed to adjoin a side surface of the first insulating film.

Abstract: A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.

Abstract: Provided are a molecular electronic device including a functional molecular active layer having a stack structure including oppositely charged first and second molecular active layers, and a method of manufacturing the molecular electronic device. The molecular electronic device includes: a first electrode; an organic dielectric thin layer comprising molecules each having a first end self-assembled on a surface of the first electrode and a second end having a cationic or anionic group; a functional molecular active layer stacked on the organic dielectric thin layer by selective self-assembly with positive and negative ions and comprising an electroactive functional group having a cyclic compound; and a second electrode formed on the functional molecular active layer.

Abstract: A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.

Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or SnO2, the substantially insulating ZnO or SnO2 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Abstract: Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor.

Abstract: A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked.

Abstract: A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.

Abstract: A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control

Abstract: Provided are an architecture for a non-volatile memory device that can increase the write efficiency for split-gate trap memory, as well as increase resistance to disturbances; and a method of manufacturing said memory device. The device includes, at least: a layered film having traps, formed on top of the semiconductor substrate; a memory gate electrode formed on top of the layered film; a word gate electrode laid out so as to contact the memory gate electrode and the substrate through an insulating film; and source and drain regions in the substrate, sandwiching the two gate electrodes. The equivalent oxide thickness of the insulating film sandwiched between the word gate electrode and the substrate is made greater where the layered film is in contact than where there is no contact.

Abstract: The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015?(B/A+B+N))?0.095 and N/(A+B+N) has a range of 0.045?(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0<(O/A)<2.0, and having a noncrystalline structure; and a step of performing an annealing treatment at 700° C. or higher on the metallic oxynitride having a noncrystalline structure to form a metallic oxynitride including a crystalline phase with a cubical crystal incorporation percentage of 80% or higher.

Abstract: Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

Abstract: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

Abstract: A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a third dielectric layer formed over the second dielectric layer. The third dielectric layer may have a high dielectric constant and may be deposited at a relatively high temperature. A control gate may be formed over the third dielectric layer.

Abstract: A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conducti

Abstract: A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.

Abstract: A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.

Abstract: A nonvolatile semiconductor memory device includes: fin-shaped control gate electrodes formed on an insulating layer; and a body layer having a channel region arranged to cross the control gate electrodes and embedded in the control gate electrodes sequentially via a first insulating layer, a charge storage layer, and a second insulating layer.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a memory unit; and a circuit unit provided between the semiconductor substrate and the memory unit. The memory unit includes: a stacked structural unit having electrode films alternately stacked with inter-electrode-film insulating films; a semiconductor pillar piercing the stacked structural unit; and a storage unit provided corresponding to an intersection between the electrode films and the semiconductor pillar. The circuit unit includes first and second transistors having different conductivity type, a first interconnect, and first and second contact plugs. The first interconnect includes silicide provided on a side of the first and second transistors opposite to the semiconductor substrate. The first contact plug made of polysilicon of the first conductivity type connects the first interconnect to the first transistor.

Abstract: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.

Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

Abstract: flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

Abstract: There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract: A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.

Abstract: The disclosure of this application enhances the data writing speed of an electrically erasable and writable semiconductor memory. In a semiconductor storage device of this application, at a time of writing data, when a positive voltage lower than a voltage at control gate 30 is applied to potential control gate 28 formed inside tunnel oxide film 360 between p channel 22 of a transistor and floating gate 32, a potential barrier between p channel 22 of the transistor and floating gate 32 is lowered, and a time required for storing an electron in floating gate 30 is reduced. After data is stored, when 0 V or a negative voltage is applied to the potential control gate, a potential barrier for an electron moving from the floating gate to the channel of the transistor increases, thereby preventing erasure of data.

Abstract: The present invention is a semiconductor device including a semiconductor substrate having a trench, a first insulating film provided on side surfaces of the trench, a second insulating film of a material different from the first insulating film provided to be embedded in the trench, a word line provided extending to intersect with the trench above the semiconductor substrate, a gate insulating film of a material different from the first insulating film separated in an extending direction of the word line by the trench and provided under a central area in a width direction of the word line, and a charge storage layer separated in the extending direction of the word line by the trench and provided under both ends in the width direction of the word line to enclose the gate insulating film, and a method for manufacturing the same.

Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.

Abstract: A semiconductor device includes a silicon substrate; an insulation layer formed on the silicon substrate, the insulation layer containing an oxide of an element of at least one kind selected from at least Hf, Zr, Ti and Ta; an electrode formed on the insulation layer; and a metal oxide layer containing La and Al, the metal oxide layer being provided at at least one of an interface between the silicon substrate and the insulation layer and an interface between the insulation layer and the electrode.

Abstract: A nonvolatile semiconductor memory device includes a plurality of bit line diffusion layers formed in a semiconductor region, and extending in a row direction; a plurality of first insulating films, each being formed on the semiconductor region and between adjacent two of the bit line diffusion layers, and including a charge trapping film; a plurality of bit line insulating films formed above the respective bit line diffusion layers; and a plurality of word lines formed above the semiconductor region to cover the first insulating films and the bit line insulating films, intersecting the bit line diffusion layers, and extending in a column direction. The bit line insulating films have smaller thicknesses than the first insulating films, and upper surfaces of the bit line insulating films are parallel to upper surfaces of the first insulating films.

Abstract: A method of manufacturing a flash memory device is disclosed. A first oxide layer, a nitride layer, a second oxide layer, and a first polysilicon layer, which is a part of a polysilicon layer for a control gate, are formed to a predetermined thickness on a semiconductor substrate. A first etch process is performed to form gate patterns. An insulating layer is formed on the entire surface. A second etch process is implemented so that insulating layer spacers are formed on both sidewalls of each gate pattern while exposing the first polysilicon layer. A second polysilicon layer for the control gate is formed on the entire surface.

Abstract: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.

Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

Abstract: A method for fabricating a capacitor in a semiconductor device includes: forming a bottom electrode; forming a ZrxAlyOz dielectric layer on the bottom electrode using an atomic layer deposition (ALD) method, wherein the ZrxAlyOz dielectric layer comprises a zirconium (Zr) component, an aluminum (Al) component and an oxygen (O) component mixed in predetermined mole fractions of x, y and z, respectively; and forming a top electrode on the ZrxAlyOz dielectric layer.

Abstract: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first conductive region and the second conductive region.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 ?m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

Abstract: A method is provided for fabricating a semiconductor device having a gate electrode overlying a gate insulator. The method, in accordance with one embodiment, comprises depositing a layer of spin on glass overlying the gate electrode, the layer of spin on glass comprising a substantially UV opaque material. The layer of spin on glass is heated to a temperature less than about 450° C., and all subsequent process steps in the fabrication of the device are limited to temperatures less than about 450° C.