Short Formed In Recess In Substrate Patents (Class 438/274)
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Patent number: 11152287Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.Type: GrantFiled: November 8, 2016Date of Patent: October 19, 2021Assignee: Mitsubishi Electric CorporationInventors: Hideo Komo, Arata Iizuka, Takeshi Omaru
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Patent number: 11031283Abstract: The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. A material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.Type: GrantFiled: November 6, 2019Date of Patent: June 8, 2021Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 10217805Abstract: Disclosed herein is a display apparatus, including, a panel having a plurality of pixels disposed in a matrix and each including a self-luminous element for emitting light, the panel including first to third conductive layers laminated in order on a supporting substrate, a first contact portion between the first and second conductive layers and a second contact portion between the second and third conductive layers being disposed at the same position in a planar direction.Type: GrantFiled: July 11, 2017Date of Patent: February 26, 2019Assignee: Sony CorporationInventors: Keisuke Omoto, Masatsugu Tomida
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Patent number: 10115343Abstract: A sub-pixel of an organic light emitting display device according to an embodiment includes an organic light emitting diode connected to a first node; a driving transistor comprising a first electrode, a second electrode connected to the first node, and a gate electrode connected to a second node; a first capacitor connected between the first node and the second node; a second capacitor connected between an emission control line and the second node; a first transistor comprising a first electrode connected to the first electrode of the driving transistor, a second electrode connected to the second node, and a gate electrode connected to a scan line; and a second transistor comprising a first electrode connected to a high potential voltage line, a second electrode connected to the first electrode of the driving transistor, and a gate electrode connected to the emission control line.Type: GrantFiled: November 28, 2016Date of Patent: October 30, 2018Assignee: LG DISPLAY CO., LTD.Inventors: DongChun Kang, JongHyun Kim
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Patent number: 9960345Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.Type: GrantFiled: February 8, 2017Date of Patent: May 1, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Ching-Tzu Chen, Joel D. Chudow
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Patent number: 9012955Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.Type: GrantFiled: June 19, 2013Date of Patent: April 21, 2015Assignee: STMicroelectronics SAInventor: Pascal Fonteneau
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Patent number: 8912070Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.Type: GrantFiled: October 12, 2012Date of Patent: December 16, 2014Assignee: The Institute of Microelectronics Chinese Academy of ScienceInventors: Xiaolong Ma, Huaxiang Yin, Zuozhen Fu
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Patent number: 8845077Abstract: A pattern forming method includes: a modification treatment step of, in accordance with a pattern to be formed on a pattern forming surface of a base body, applying a light beam having a width smaller than a diameter of each of dots to constitute the pattern, onto a treatment target region including at least outer edges on both sides in a width direction of a region where the pattern is to be formed in the pattern forming surface, thereby carrying out modification treatment on the treatment target region; and a droplet deposition step of ejecting and depositing droplets of a functional liquid by an inkjet method onto the region where the pattern is to be formed including the treatment target region where the modification treatment has been carried out.Type: GrantFiled: March 14, 2013Date of Patent: September 30, 2014Assignee: FUJIFILM CorporationInventor: Jun Kodama
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Patent number: 8735228Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: GrantFiled: September 5, 2013Date of Patent: May 27, 2014Assignee: PFC Device Corp.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Patent number: 8703563Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: July 26, 2012Date of Patent: April 22, 2014Assignee: Alpha & Omega Semiconductor LtdInventors: François Hébert, Anup Bhalla
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Patent number: 8518777Abstract: A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.Type: GrantFiled: April 8, 2011Date of Patent: August 27, 2013Assignee: Fairchild Semiconductor CorporationInventor: Praveen Muraleedharan Shenoy
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Publication number: 20130210205Abstract: The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.Type: ApplicationFiled: July 19, 2012Publication date: August 15, 2013Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
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Patent number: 8497528Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.Type: GrantFiled: May 6, 2010Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
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Patent number: 8486808Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode material that covers a gate insulating film formed on each of side surfaces of first and second silicon pillars, wherein a film formation amount of the gate electrode material is controlled so that a first part with which the side surface of the first silicon pillar is covered via the gate insulating film does not contact with a second part with which the side surface of the second silicon pillar is covered via the gate insulating film. The method further includes: forming a mask insulating film that covers the first and second parts and fills a region between the first and second parts; and etching the gate electrode material using the mask insulating film as a mask, thereby forming gate electrodes with which the side surfaces of the first and second silicon pillars are covered via the gate insulating film, respectively and a conductive film electrically connecting the gate electrodes to each other.Type: GrantFiled: April 20, 2011Date of Patent: July 16, 2013Assignee: Elpida Memory, Inc.Inventor: Kazuhiro Nojima
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Patent number: 8435860Abstract: A fabrication method for a trench type semiconductor device includes: forming a first base layer; forming a gate insulating film on a bottom and sidewall surfaces of a trench; forming a gate electrode for filling up into the trench; covering the gate electrode and forming an interlayer insulating film; forming a second base layer on the first base layer; forming a first main electrode layer on the second base layer; forming a first main electrode which passes through the first main electrode layer by applying the interlayer insulating film as a mask, is connected to the second base layer in the bottom surface of a self-aligned contact trench, and is connected to the first main electrode layer of the self-aligned contact trench; forming a second main electrode layer at a back side of the first base layer; and forming a second main electrode at the second main electrode layer.Type: GrantFiled: April 30, 2012Date of Patent: May 7, 2013Assignee: Rohm Co., Ltd.Inventor: Kenichi Yoshimochi
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Publication number: 20130049101Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen Chu HSIAO, Ju Wen HSIAO, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
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Patent number: 8372716Abstract: In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device.Type: GrantFiled: May 2, 2011Date of Patent: February 12, 2013Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, Peter J. Zdebel
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Patent number: 8017469Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: GrantFiled: January 21, 2009Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tien-Ying Luo, Gauri V. Karve, Daniel G. Tekleab
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Patent number: 7951661Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.Type: GrantFiled: December 28, 2007Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Hee Sang Kim
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Patent number: 7936008Abstract: An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.Type: GrantFiled: May 2, 2008Date of Patent: May 3, 2011Assignee: Fairchild Semiconductor CorporationInventor: Praveen Muraleedharan Shenoy
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Patent number: 7713822Abstract: A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions.Type: GrantFiled: October 10, 2008Date of Patent: May 11, 2010Assignee: Fairchild Semiconductor CorporationInventors: Paul Thorup, Ashok Challa, Bruce Douglas Marchant
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Patent number: 7679146Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.Type: GrantFiled: May 30, 2006Date of Patent: March 16, 2010Assignee: Semiconductor Components Industries, LLCInventors: Shanghui Larry Tu, Gordon M. Grivna
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Patent number: 7651917Abstract: In the present invention, an npn junction is formed by circularly forming a p? type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated.Type: GrantFiled: September 9, 2008Date of Patent: January 26, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Mamoru Kaneko
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Patent number: 7651918Abstract: Semiconductor structures (52-9, 52-11, 52-12) and methods (100-300) are provided for a semiconductor devices employing strained (70) and relaxed (66) semiconductors, The method comprises, forming (106, 208, 308) on a substrate (54, 56, 58) first (66-1) and second (66-2) regions of a first semiconductor material (66) of a first conductivity type and a first lattice constant spaced apart by a gap or trench (69), filling (108, 210, 308) the trench or gap (69) with a second semiconductor material (70) of a second, conductivity type and a second different lattice constant so that the second semiconductor material (70) is strained with respect to the first semiconductor material (66) and forming (110, 212, 312) device regions (80, 88, S, G, D) communicating with the first (66) and second (70) semiconductor materials and adapted to provide device current (87, 87?) through at least part of the strained second semiconductor material (70) in the trench (69).Type: GrantFiled: August 25, 2006Date of Patent: January 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Edouard D. de Frésart, Robert W. Baird
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Patent number: 7648878Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.Type: GrantFiled: December 20, 2005Date of Patent: January 19, 2010Assignee: Hynix Semiconductor Inc.Inventor: Tae-Woo Jung
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Patent number: 7615449Abstract: The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.Type: GrantFiled: September 29, 2006Date of Patent: November 10, 2009Assignee: Hynix Semiconductor Inc.Inventors: Sung Woong Chung, Sang Don Lee
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Patent number: 7598114Abstract: A method of forming an air gap within a semiconductor structure by the steps of: (a) using a sacrificial polymer to occupy a space in a semiconductor structure; and (b) heating the semiconductor structure to decompose the sacrificial polymer leaving an air gap within the semiconductor structure, wherein the sacrificial polymer of step (a) is: (a) a copolymer of 5-ethylidene-2-norbornene and vinylbenzocyclobutene (or a vinylbenzocyclobutene derivative); or (b) a copolymer of 5-ethylidene-2-norbornene and 5-(3benzocyclobutylidene)-2-norbornene; or (c) a polymer of 5-(3benzocyclobutylidene)-2-norbornene. In addition, a semiconductor structure, having a sacrificial polymer positioned between conductor lines, wherein the sacrificial polymer is: (a) a copolymer of 5-ethylidene-2-norbornene and vinylbenzocyclobutene (or a vinylbenzocyclobutene derivative); or (b) a copolymer of 5-ethylidene-2-norbornene and 5-(3benzocyclobutylidene)-2-norbornene; or (c) a polymer of 5-(3benzocyclobutylidene)-2-norbornene.Type: GrantFiled: January 30, 2004Date of Patent: October 6, 2009Inventors: Youngfu Li, Robert A. Kirchhoff, Jason Q. Niu, Kenneth L. Foster
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Patent number: 7572706Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.Type: GrantFiled: February 28, 2007Date of Patent: August 11, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Da Zhang, Brian A. Winstead
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Patent number: 7566622Abstract: A method of fabricating a power semiconductor device in which contact trenches are formed prior to forming the gate trenches.Type: GrantFiled: June 5, 2006Date of Patent: July 28, 2009Assignee: International Rectifier CorporationInventor: Adam I Amali
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Patent number: 7556995Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.Type: GrantFiled: November 27, 2006Date of Patent: July 7, 2009Assignees: STMicroelectronics Crolles 2 SAS, Commissariat a l'Energie AtomiqueInventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
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Patent number: 7465622Abstract: A method for fabricating a vertical channel transistor device is provided. An opening is formed in a dielectric stack comprised of a pad nitride layer and a pad oxide layer. A plurality of epitaxial silicon growth and dry etching processes are carried out to form drain, vertical channel and source in the opening. Subsequently, sidewall gate dielectric and sidewall gate electrode are formed on the vertical channel. The present invention is suited for dynamic random access memory (DRAM) devices, particularly suited for very high-density trench-capacitor DRAM devices.Type: GrantFiled: September 29, 2006Date of Patent: December 16, 2008Assignee: Nanya Technology Corp.Inventor: Shian-Jyh Lin
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Publication number: 20080233696Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: February 22, 2008Publication date: September 25, 2008Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7411266Abstract: In one embodiment, a semiconductor device is formed having charge compensation trenches in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.Type: GrantFiled: May 30, 2006Date of Patent: August 12, 2008Assignee: Semiconductor Components Industries, L.L.C.Inventors: Shanghui Larry Tu, Gordon M. Grivna
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Patent number: 7361585Abstract: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).Type: GrantFiled: January 27, 2005Date of Patent: April 22, 2008Assignee: Advantech Global, LtdInventors: Thomas P. Brody, Joseph A. Marcanio
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Patent number: 7354786Abstract: A micromechanical sensor element and a method for the production of a micromechanical sensor element that is suitable, for example in a micromechanical component, for detecting a physical quantity. Provision is made for the sensor element to include a substrate, an access hole and a buried cavity, at least one of the access holes and the cavity being produced in the substrate by a trench etching and/or, in particular, an isotropic etching process. The trench etching process includes different trenching (trench etching) steps which may be divided into a first phase and a second phase. Thus, in the first phase, at least one first trenching step is carried out in which, in a predeterminable first time period, material is etched out of the substrate and a depression is produced. In that trenching step, a typical concavity is produced in the wall of the depression.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Stefan Finkbeiner, Matthias Illing, Frank Schaefer, Simon Armbruster, Gerhard Lammel, Christoph Schelling, Joerg Brasas
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Patent number: 7344943Abstract: A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.Type: GrantFiled: April 20, 2005Date of Patent: March 18, 2008Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
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Patent number: 7338864Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.Type: GrantFiled: March 20, 2006Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventors: Eung-Rim Hwang, Se-Aug Jang, Tae-Woo Jung, Seo-Min Kim, Woo-Jin Kim, Hyung-Soon Park, Young-Bog Kim, Hong-Seon Yang, Hyun-Chul Sohn
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Patent number: 7332396Abstract: A semiconductor device with a recessed channel and a method of fabricating the same are provided. The semiconductor device comprises a substrate, a gate, a source, a drain, and a reverse spacer. The substrate comprises a recessed trench. The gate is formed above the recessed trench and extends above the substrate. The gate further comprises a polysilicon layer and a conductive layer; wherein the polysilicon layer is formed inside the recessed trench of the substrate, and the conductive layer is formed above the polysilicon layer and extends above the substrate. Moreover, the width of the conductive layer increases gradually bottom-up. The source and the drain are formed respectively at two sides of the gate. The reverse spacer is formed above the polysilicon layer and against the sidewall of the conductive layer.Type: GrantFiled: July 10, 2006Date of Patent: February 19, 2008Assignee: Promos Technologies Inc.Inventors: Jim Lin, San-Jung Chang, Yu-Cheng Lo
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Patent number: 7314792Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.Type: GrantFiled: December 30, 2005Date of Patent: January 1, 2008Assignee: Hynix Semiconductor Inc.Inventors: Myung-Ok Kim, Tae-Woo Jung, Sung-Kwon Lee, Sea-Ug Jang
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Patent number: 7282412Abstract: The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon.Type: GrantFiled: May 25, 2005Date of Patent: October 16, 2007Assignee: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Wayne B. Grabowski
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Patent number: 7029977Abstract: A fabrication method of a semiconductor wafer can fill trenches formed in a semiconductor substrate with an epitaxial film with high crystal quality without leaving cavities in the trenches. The trenches are formed in the first conductivity type semiconductor substrate. Planes exposed inside the trenches are made clean surfaces by placing the substrate in a gas furnace, followed by supplying the furnace with an etching gas and carrier gas, and by performing etching on the exposed planes inside the trenches by a thickness from about a few nanometers to one micrometer. The trenches have a geometry opening upward through the etching. Following the etching, a second conductivity type semiconductor is epitaxially grown in the trenches by supplying the furnace with a growth gas, etching gas, doping gas and carrier gas, thereby filling the trenches. Instead of making the trenches slightly-opened upward, their sidewalls may be made planes enabling facet formation.Type: GrantFiled: March 5, 2004Date of Patent: April 18, 2006Assignees: Fuji Electric Holdings Co., Ltd., Shin-Etsu Handotai Co., Ltd.Inventors: Daisuke Kishimoto, Susumu Iwamoto, Katsunori Ueno, Ryohsuke Shimizu, Satoshi Oka
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Patent number: 7005352Abstract: A trench-type lateral power MOSFET is manufactured by forming an n?-type diffusion region, which will be a drift region, on a p?-type substrate; selectively removing a part of substrate and a part of n?-type diffusion region to form trenches; forming a gate oxide film of 0.05 ?m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p?-type base region and an n+-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n+-type diffusion region, which will be a drain region, in the surface portion of n?-type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.Type: GrantFiled: July 21, 2004Date of Patent: February 28, 2006Assignee: Fuji Electric Co., Inc.Inventors: Naoto Fujishima, Akio Sugi, C. Andre T. Salama
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Patent number: 6977203Abstract: A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.Type: GrantFiled: November 20, 2001Date of Patent: December 20, 2005Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Brian D. Pratt
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Patent number: 6940126Abstract: A semiconductor component has at least one first terminal zone of a first conductivity type in a semiconductor body. The first terminal zone is contact-connected by a first terminal electrode. A drift zone of the first conductivity type is adjoined by a second terminal zone of the second conductivity type. A channel zone of a second conductivity type is formed between the at least one first terminal zone and the drift zone. A control electrode is insulated from the semiconductor body and adjacent to the channel zone. A first channel is formed by the channel zone in a region adjacent to the control electrode, the first channel conducts only upon application of a control voltage that is not equal to zero between the control electrode and the first terminal zone. The first terminal electrode is connected to the drift zone via at least one second channel of the first conductivity type, which already conducts in the event of a control voltage equal to zero.Type: GrantFiled: September 4, 2003Date of Patent: September 6, 2005Assignee: Infineon Technologies AGInventors: Gerald Deboy, Uwe Wahl, Armin Willmeroth
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Patent number: 6916745Abstract: In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.Type: GrantFiled: May 20, 2003Date of Patent: July 12, 2005Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
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Patent number: 6875657Abstract: A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird's beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.Type: GrantFiled: March 26, 2002Date of Patent: April 5, 2005Assignee: Siliconix incorporatedInventors: Christiana Yue, Mohamed N. Darwish, Frederick P. Giles, Kam Hong Lui, Kuo-In Chen, Kyle Terrill, Deva N. Pattanayak
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Patent number: 6855581Abstract: The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate.Type: GrantFiled: May 23, 2002Date of Patent: February 15, 2005Assignee: Electronics and Telecommunications Research InstituteInventors: Tae Moon Roh, Dae Woo Lee, Yil Suk Yang, Il Yong Park, Sang Gi Kim, Jin Gun Koo, Jong Dae Kim
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Publication number: 20040097038Abstract: A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.Type: ApplicationFiled: July 3, 2003Publication date: May 20, 2004Inventors: Daniel M. Kinzer, Zhijun Qu, Kenneth Wagers
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Patent number: 6639275Abstract: A semiconductor device improves the gate withstand voltage of vertical MOSFETs and raises their operation speed. The gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that exposes the connection portion of the gate electrode, where the connection portion is located in the trench. The conductive plug is filled in the contact hole of the interlayer dielectric layer in such a way as to contact the connection portion of the gate electrode. The wiring layer is formed on the interlayer dielectric layer in such a way as to contact the plug, resulting in the wiring layer electrically connected to the connection portion by way of the plug. There is no need to form a connection portion for the gate electrode outside of the trench, which means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur.Type: GrantFiled: June 10, 2002Date of Patent: October 28, 2003Assignee: NEC CorporaitonInventor: Hitoshi Ninomiya
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Patent number: 6432775Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.Type: GrantFiled: June 1, 2001Date of Patent: August 13, 2002Assignee: General Semiconductor, Inc.Inventor: Richard A. Blanchard