Source/drain stressor and method therefor
A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.
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1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to semiconductor devices having source/drain stressors.
2. Related Art
Source/drain stressors have been developed to provide strain in channel regions to improve transistor performance. Tensile stress applied to the channel has been found to improve electron mobility for N channel transistors while compressive stress applied to the channel has been found to improve hole mobility. The degree of improvement is generally greater with greater stress being applied. The source/drain stressor approach involves removing the semiconductor material near the channel area to form recess regions there and then filling recess regions by growing a semiconductor material of a different type. With silicon being the starting semiconductor material, which is typical, the tensile stress can be exerted by growing silicon carbon and the compressive can be exerted by growing silicon germanium. One limitation on the stress is the carbon and germanium concentrations. Increasing these concentrations increases the stress but also increases the likelihood of dislocations. Dislocations reduce the stress. So the carbon and germanium concentrations are as a large as possible that do not result in forming dislocations. Transistor performance, however, would be improved with further increases in strain without creating other problems such as increasing transistor leakage.
Thus, there is a need for further improving the performance of devices with source/drain stressors.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
An angled implant is performed from the source side of a transistor to form a source implant region that is at least nearly under the edge of the gate. The gate has a thin sidewall spacer at the time of the implant. The gate acts as a mask for the drain side so that the doped region formed on the drain side by the implant is spaced from the gate. A subsequent anneal ensures that the source side doped region is at least aligned to the edge of the gate and may extend under the gate a small amount. An etch removes semiconductor material using the gate and sidewall spacer as a mask to form one recess region aligned on the source with the thin sidewall spacer and another recess region aligned on the drain side with the thin sidewall spacer. Forming the recess region on the drain side removes the doped region formed by the implant on the drain side. The source implant region, however, has a portion that extends under the sidewall spacer so that it is not removed by forming the source side recess region. A semiconductor material of a different type is then grown in the recess regions. This different semiconductor material then contacts the remaining portion of the source implant region and also forms a drain on the drain side. The different semiconductor material is preferably in situ doped to avoid the need for a source/drain implant that would tend to relax the strain. The remaining portion of the source implant region thus ensures that source extends at least to the edge of the gate. This is of minimal consequence on the drain side because a voltage applied to the drain will tend to deplete the region immediately adjacent to the drain anyway. Further, having it on the drain side would increase the overall parasitic capacitance. This is better understood by the following description and the drawings.
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In another embodiment, a drain side protection layer is applied for forming doped regions on only the source side after gate stack formation. Shown in
By now it should be appreciated that there a semiconductor device having stressors close to the channel which avoids the gate dielectric from being exposed to a clean in preparation for growing the stressors. One stressor is actually as close to the channel as possible because it is at the drain-channel interface, and the other stressor is only separated from the channel by a small distance, about the thickness of sidewall spacer 24. This close proximity to the channel increases the stress as compared to stressors that are further from the channel.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, other materials may be used. The semiconductor layer could itself be multiple layers. One such example would be a silicon layer with a SiGe layer immediately over the silicon layer. In such case the etch which forms the recesses would remove both SiGe and silicon. SiGe may be regrown replacing the combination of silicon and SiGe. Also indium or BF2 may be used for P type doping and antimony may be used for N type doping. Also the dimensions given are exemplary and other dimensions may be used. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Claims
1. A method for forming a semiconductor device, comprising:
- forming a gate structure overlying a substrate having a first conductivity type;
- forming a sidewall spacer adjacent to the gate structure;
- performing an angled implant in a direction of a source side of the semiconductor device to form a region on the source side, in the substrate, and under a portion of the gate structure wherein the angled implant uses dopants that cause a second conductivity type opposite to that of the first conductivity type;
- annealing the semiconductor device;
- forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material and to leave a portion of the region of the second conductivity type that is under the gate structure; and
- epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a natural lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.
2. The method of claim 1 further comprising performing in-situ doping into the second type of semiconductor material using an in-situ doping material.
3. The method of claim 2, wherein the angled implant is performed at an angle of 5 degrees to 30 degrees relative to a vertical axis.
4. The method of claim 2, wherein the semiconductor device is a P-channel device and wherein the doping material comprises one of a group consisting of Boron, BF2, and Indium, and wherein the second type of semiconductor material is silicon germanium.
5. The method of claim 2, wherein the semiconductor device is an N-channel device and wherein the doping material comprises one of a group consisting of Phosphorous, Arsenic, and Antimony, and wherein the second type of semiconductor material is silicon carbon.
6. The method of claim 2, wherein the semiconductor device is a P-channel device and wherein the in-situ doping material is Boron.
7. The method of claim 2, wherein the semiconductor device is an N-channel device and wherein the in-situ doping material comprises one of a group consisting of Phosphorous and Arsenic.
8. The method of claim 1, wherein the annealing step is performed after epitaxially growing the second type of semiconductor material in the recesses.
9. The method of claim 1, wherein the sidewall spacer has a width in a range of 40 Angstroms to 100 Angstroms.
10. The method of claim 1 further comprising forming source/drain portions corresponding to the semiconductor device and forming silicide layers over the source/drain portions and the gate structure.
11. The method of claim 1, wherein the angled implant is performed into the substrate in a manner that a doping material is implanted into a region underlying at least the sidewall spacer on only the source side of the semiconductor device.
12. A method for forming a semiconductor device, comprising:
- forming a gate structure overlying a substrate;
- forming a sidewall spacer adjacent to the gate structure;
- patterning a photoresist layer such that a drain side of the semiconductor device is covered, but a source side of the semiconductor device is exposed;
- performing an implant into the substrate;
- removing the photoresist layer;
- annealing the semiconductor device;
- forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material; and
- epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device, wherein the second type of semiconductor material is in situ doped into the second type of semiconductor material during the epitaxially growing.
13. The method of claim 12, wherein the semiconductor device is a P-channel device and wherein the doping material comprises one of a group consisting of Boron, BF2, and Indium, and wherein the second type of semiconductor material is silicon germanium.
14. The method of claim 12, wherein the semiconductor device is an N-channel device and wherein the doping material comprises one of a group consisting of Phosphorous, Arsenic, and Antimony, and wherein the second type of semiconductor material is silicon carbon.
15. The method of claim 12, wherein the annealing step is performed after epitaxially growing the second type of semiconductor material in the recesses.
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Type: Grant
Filed: Feb 28, 2007
Date of Patent: Aug 11, 2009
Patent Publication Number: 20080203449
Assignee: Freescale Semiconductor, Inc. (Austin, TX)
Inventors: Da Zhang (Austin, TX), Brian A. Winstead (Austin, TX)
Primary Examiner: Charles D. Garber
Assistant Examiner: Mohsen Ahmadi
Attorney: James L. Clingan, Jr.
Application Number: 11/680,181
International Classification: H01L 21/336 (20060101); H01L 21/8236 (20060101);