Abstract: Double diffused MOS (DMOS) transistors feature extended drain regions to provide depletion regions which drop high drain voltages to lower voltages at the gate edges. DMOS transistors exhibit lower drain breakdown potential in the on-state than in the off-state than in the off-state due to snapback by a parasitic bipolar transistor that exists in parallel with the DMOS transistor. The instant invention is a cascoded DMOS transistor in an integrated circuit incorporating an NMOS transistor on the DMOS source node to reverse bias the parasitic emitter-base junction during on-state operation, eliminating snapback. The NMOS transistor may be integrated with the DMOS transistor by connections in the interconnect system of the integrated circuit, or the NMOS transistor and DMOS transistor may be fabricated in a common p-type well and integrated in the IC substrate. Methods of fabricating an integrated circuit with the incentive cascoded DMOS transistor are also disclosed.

Abstract: First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.

Abstract: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.

Abstract: A manufacturing method of semiconductor device includes: forming a nitride film above a silicon substrate including a first region and a second region which respectively correspond to an outside of a memory cell region and the memory cell region; forming trenches reaching from the nitride film to the silicon substrate; retreating the nitride film such that widths of the trenches at the nitride film become wider; forming a buried oxide film to be buried in the trenches after the retreating; polishing the buried oxide film with the nitride film being used as a stopper; removing the nitride film after the polishing; implanting impurity after the removing; forming gate electrodes after the implanting; and implanting impurity after the forming the gate electrodes.

Abstract: A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the first dopant region, growing a first isolation region over a first portion of the substrate, the first dopant region, and the second dopant region, growing a second isolation region over a second portion of the substrate, the first dopant region, and the second dopant region, defining a contact region in the second dopant region, the contact region extending between the first isolation region and the second isolation region, depositing a gate oxide layer to form a first gate dielectric atop the first isolation region and a portion of the contact region, and overlaying a gate conductive layer on top of the gate oxide layer to form a first gate conductor atop the first gate dielectric.

Abstract: A photo sensor has an insulator layer for covering a diode stack, and the insulator layer is made of phtoresist to reduce a side leakage current.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: A method for making a semiconductor structure of a memory device includes forming a capacitor having a gate dielectric between a gate conductor and a dopant region of a first conductivity type located in another dopant region of a second conductivity type, forming a bipolar transistor having a base region of the first conductivity type, and forming a field-effect transistor having a gate conductor coupled to the gate conductor of the capacitor, wherein the dopant region and the base region of the first conductivity type are formed in the same step to avoid additional cost in forming the capacitor.

Abstract: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist layer 16 as a mask via the oxidation film 14a. When the oxidation films 14a and 14b are used as sacrificing oxidation films, gate oxidation films are formed in the element holes 12a and 12b after removing the resist film 16 and the oxidation films 14a and 14b. When the oxidation films 14a and 14b are used as gate oxidation films, the oxidation films are once thinned by etching and then thickened after removing the resist layer 16. The gate oxidation film 14a is thicker than the gate oxidation film 14b by forming the ion implantation layer 18.

Abstract: A semiconductor device includes a substrate of a first type of conductivity provided with at least one gate on one of its faces, and at least two doped regions of a second type of conductivity for forming a drain region and a source region. The two doped regions are arranged in the substrate flush with the face of the substrate on each side of a region of the substrate located under the gate for forming a channel between the drain and source regions. At least one region of doping agents of the second type of conductivity is implanted only in the channel.

Abstract: The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.

Abstract: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

Abstract: An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cells and the FETs are made up of a spacer material with local charge storage nodes that is capable of storing electrical charge (e.g., silicon-nitride with traps or oxide with silicon nanocrystals). The source/drain regions of the NVM cells omit lightly-doped drains (which are used in the CMOS FETs), and the NVM cells are formed with thinner sidewall oxide layers than the CMOS FETs to facilitate programming/erasing operations. A production method includes a modified CMOS process flow where the CMOS FET gate structures receive different source/drain diffusions and oxides than the NVM gate structures, but both receive substantially identical sidewall spacers, which are used as charge storage structures in the NVM cells.

Abstract: The method includes forming a 1-10000 nm thick SiO2, HfO2, Al2O3 and/or quartz gate dielectric on an Si back gate. An Al or Mo gate electrode is formed on the gate dielectric. An Al2O3 insulating layer is formed over the gate electrode. A C, Si, GaAs, InP, and/or InGaAs nanotube is formed on the insulating layer and gate dielectric. The nanotube has a central region on the insulating layer above the gate electrode and first and second ends on the gate dielectric. A source is formed on the first end and spaced from the central region and gate electrode by a first peripheral region. A drain is formed on the second end and spaced from the central region and gate electrode by a second peripheral region. The first and second peripheral regions are doped with Cl2, Br2, K, Na, or a molecule of polyethylenimine using wet deposition or evaporation.

Abstract: A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate.

Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

Abstract: By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process complexity and also not affecting the further processing of the semiconductor device. Hence, a high degree of flexibility may be provided with respect to enhancing transistor performance in a highly local manner.

Abstract: A substrate is provided, and a sacrificial pattern having an opening partially exposing a high voltage device region is formed on the substrate. Subsequently, a gate oxide layer is formed in the opening, and the sacrificial pattern is removed. A gate electrode, and two heavily doped regions are formed. Than, a salicidation process is carried out to form salicides on the surface of the gate electrode and the heavily doped regions.

Abstract: Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

Abstract: A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Abstract: By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.

Abstract: A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern.

Abstract: The present invention provides a silicon carbide semiconductor device comprising a semiconductor substrate comprising silicon carbide, which contains a first conductivity type impurity diffused therein in a high concentration, a semiconductor layer formed over the semiconductor substrate and containing the first conductivity type impurity diffused therein in a low concentration, a plurality of well regions formed on a front surface side of a cell forming area set to the semiconductor layer and in which a second conductivity type impurity corresponding to a type opposite to the first conductivity type impurity is diffused, source layers formed on the front surface side lying within the well regions and each containing the first conductivity type impurity diffused therein in a high concentration, an outer peripheral insulating film thick in thickness, which is formed over the semiconductor layer in an outer peripheral area that surrounds the cell forming area, a gate oxide film formed over the front surface of

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.

Abstract: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive type; and first to third ion implantation processes sequentially executed for controlling threshold voltages corresponding to each transistor formed on the semiconductor substrate the first semiconductor region, and the second semiconductor region respectively. The first ion implantation process is executed in a high-threshold low-voltage transistor forming region of the first semiconductor region after forming the first semiconductor region. The second ion implantation process is executed in a high-threshold low-voltage transistor forming region of the second semiconductor region.

Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A transistor which may effectively control the short channel effect with a vertical transistor structure. This structure may prevent the degradation of a transistor's performance caused by the hot carrier effect. The transistor has a source region having a concentration of implanted impurity ions on a semiconductor substrate; a channel region having a cylindrical shape over the source region; a drain region formed over the channel region; a gate insulation layer formed over the source region, a side of the channel region, and the drain region; and a gate conductor extending over an upper portion and one side of the channel region.

Abstract: A method of performing ion implantation method for a high-voltage device. The method includes defining a logic region and a high-voltage region in a semiconductor substrate, forming a first gate insulation layer on the semiconductor substrate in the logic region and a second gate insulation layer on the semiconductor substrate in the high-voltage region, the second gate insulation layer being thicker than the first gate insulation layer, forming a hollow region in the logic region and a source region in the high-voltage region by implanting first conductive impurities into the logic region and source regions of the semiconductor substrate, and forming a second conductive impurity layer in the logic region by implanting second conductive impurities logic region of the into the semiconductor substrate.

Abstract: The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Abstract: A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region of a CMOS imager photodiode are disclosed. The channel impurity gradient in the transfer gate provides a complete charge transfer between the charge collection region of the photodiode and a floating diffusion node. The dopant gradient region is formed by doping a region at one end of the channel with a low enhancement dopant and another region at the other end of the channel with a high enhancement dopant.

Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

Abstract: A nonvolatile semiconductor memory device capable of improving injection efficiency and simplifying manufacturing process is provided. The device comprises a memory cell having second conductive type of first impurity diffusion area and second impurity diffusion area on a first conductive type of semiconductor substrate, between the first and second impurity diffusion areas, a first laminate section formed by laminating a first insulating film, a charge storage layer, a second insulating film and a first gate electrode in this order from the bottom, and a second laminate section formed by laminating a third insulating film and a second gate electrode in this order from the bottom, wherein an area sandwiched between the first and second laminate sections is the second conductive type of a third impurity diffusion area having impurity density lower than that of the first and second impurity diffusion areas and not higher than 5×1012 ions/cm2.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity concentration of at least one of the string selection transistor and the ground selection transistor.

Abstract: Under a sidewall formed over a side wall of a gate electrode, a low-concentration LDD region and a high-concentration LDD region which is extremely shallow and apart from a region under the gate electrode are formed. Further, a source/drain region is formed outside these LDD regions. Since the extremely shallow high-concentration LDD region is formed under the sidewall, even if hot carriers are accumulated in the sidewall, depletion due to the hot carriers can be suppressed. Further, since the high-concentration LDD region is formed apart from a region under the gate electrode, a transverse electric field in the channel is sufficiently relaxed, so that characteristic deterioration due to a threshold shift can be suppressed.

Abstract: Embodiments relate to an ion implantation method wherein a semiconductor substrate is divided into a core region, a high voltage region, and an I/O region. The core region and the I/O region are divided into a PMOS transistor region for forming PMOS transistors and an NMOS transistor region for forming NMOS transistors. The ion implantation method includes performing a first ion implantation process employing a first process condition on the NMOS transistor region of the substrate using a first mask, thus setting threshold voltages for the NMOS transistor region of the I/O region and for the high voltage region at the same time. A second ion implantation process employs a second process condition on the NMOS transistor region of the substrate using a second mask, thus setting a threshold voltage for the core region.

Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

Abstract: A method of forming a semiconductor device may include forming a semiconductor structure on a substrate wherein the semiconductor structure defines a mesa having a mesa surface opposite the substrate and mesa sidewalls between the mesa surface and the substrate. A first passivation layer can be formed on at least portions of the mesa sidewalls and on the substrate adjacent the mesa sidewalls wherein at least a portion of the mesa surface is free of the first passivation layer and wherein the first passivation layer comprises a first material. A second passivation layer can be formed on the first passivation layer wherein at least a portion of the mesa surface is free of the second passivation layer, and wherein the second passivation layer comprises a second material different than the first material. Related devices are also discussed.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p? type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p? type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Abstract: A semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.