Buried Channel Patents (Class 438/282)
  • Patent number: 11239074
    Abstract: Devices comprising germanium nanosheets are described herein. Methods of forming such germanium nanosheets and devices including such germanium nanosheets are also described.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 1, 2022
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventor: Hung-Hsiang Cheng
  • Patent number: 11158711
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A passivation layer may be above the channel layer and between the source electrode and the drain electrode, and a top dielectric layer may be above the gate electrode, the channel layer, the source electrode, the drain electrode, and the passivation layer. In addition, an air gap may be above the passivation layer and below the top dielectric layer, and between the source electrode and the drain electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Li Huey Tan, Tristan Tronic, Benjamin Chu-Kung
  • Patent number: 11133421
    Abstract: A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Seung Yang, Eun Hye Choi, Seung Mo Kang, Yong Seung Kim, Jung Taek Kim, Min-Hee Choi
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10868117
    Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 15, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Po-Hao Tseng
  • Patent number: 10651288
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz
  • Patent number: 10605768
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10510837
    Abstract: Structures, devices and methods are provided for forming nanowires on a substrate. A first protruding structure is formed on a substrate. The first protruding structure is placed in an electrolytic solution. Anodic oxidation is performed using the substrate as part of an anode electrode. One or more nanowires are formed in the protruding structure. The nanowires are surrounded by a first dielectric material formed during the anodic oxidation.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 17, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Po-Hao Tseng
  • Patent number: 10153170
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa Jin Jang, Jae Young Park, Sun Young Lee, Ha Kyu Seong, Han Mei Choi
  • Patent number: 10134840
    Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Chun-Chen Yeh, Xiuyu Cai, Qing Liu, Ruilong Xie
  • Patent number: 10068794
    Abstract: A system and method for fabricating non-planar devices while managing semiconductor processing yield and cost are described. A semiconductor device fabrication process forms a stack of alternating semiconductor layers. A trench is etched and filled with at least an oxide layer with a length at least that of a device channel length while being bounded by sites for a source region and a drain region. The process places a second silicon substrate on top of both the oxide layer in the trench and the top-most semiconducting layer of the stack. The two surfaces making contact by wafer bonding use the same type of semiconducting layer. The device is flipped such that the first substrate and the stack are on top of the second substrate. The process forms nanowires of a gate region from the stack in the top first substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 4, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 9905643
    Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9842835
    Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor and diode regions. The method further includes depositing a mask, where the mask covers only the field-effect transistor region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the field-effect transistor region, and depositing a metal over the substrate to create terminals.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9704992
    Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio s
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: July 11, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven
    Inventors: Anne Verhulst, Devin Verreck, AliReza Alian
  • Patent number: 9484271
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama, Yoshiki Yamamoto
  • Patent number: 9425259
    Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9362397
    Abstract: A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 7, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Gi Hur, Sangsu Kim, Junggil Yang, Changjae Yang, Dongkyu Lee
  • Patent number: 9324812
    Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Sang-Su Kim, Sung-Gi Hur
  • Patent number: 9263295
    Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
  • Patent number: 9153587
    Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: October 6, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Stanley Seungchul Song
  • Patent number: 9123567
    Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Ravi Pillarisetty, Gilbert Dewey, Niloy Mukherjee, Jack Kavalieros, Willy Rachmady, Van Le, Benjamin Chu-Kung, Matthew Metz, Robert Chau
  • Patent number: 9029211
    Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 12, 2015
    Assignee: Semicoductor Manufacturing International (Shanghai) Corporation
    Inventor: Deyuan Xiao
  • Patent number: 8999792
    Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Stanley Seungchul Song
  • Patent number: 8987794
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 24, 2015
    Assignee: Intel Coporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Patent number: 8981490
    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • Publication number: 20150035053
    Abstract: Semiconductor devices and methods for manufacturing an LDMOS FinFET integrated circuit. The intermediate semiconductor device includes a substrate, a first well in the substrate, a second well in the substrate, and at least two polysilicon gates. The first well overlaps the second well and the at least one first gate is disposed over the first well and at least one second gate is disposed over the second well. The method includes forming a channel region and a drift region in the substrate, wherein the channel region overlaps the drift region, forming a shallow trench isolation region in the drift region, forming at least one first gate over the channel region, forming at least one second gate over the shallow trench isolation region, and applying at least one metal layer over the at least one first gate and the at least one second gate.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Jagar SINGH
  • Patent number: 8946679
    Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventor: Ravi Pillarisetty
  • Patent number: 8946027
    Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Publication number: 20150015337
    Abstract: In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventors: ALI ESHRAGHI, ALFREDO TOMASINI
  • Patent number: 8927356
    Abstract: Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 6, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tsung-Liang Chen, Hsin-Neng Tai, Huey-Ming Wang, Puneet Khanna
  • Patent number: 8916032
    Abstract: The present invention discloses an improved method of LED reflector manufacturing process where the method includes providing a substrate, wherein said substrate comprises a reflector unit, and a Light Emitting Diode; providing a shield member with ferromagnetic property; placing said shield member over the desired area of over the substrate; providing a magnet where said shield member is attracted to; placing said magnet immediately below the substrate wherein said magnet is capable of immobilizing the shield member over the substrate; performing a vacuum deposition coating; and removing the magnet and the shield member.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 23, 2014
    Inventors: Roger Wen Yi Hsu, Shu-Yu Hsu, Shu-His Hsu
  • Patent number: 8871592
    Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8836028
    Abstract: In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: September 16, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Dwayne S. Reichl, Harold Heidenreich
  • Publication number: 20140239392
    Abstract: A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n?-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.
    Type: Application
    Filed: June 7, 2012
    Publication date: August 28, 2014
    Inventors: Daisuke Matsumoto, Naoki Tega, Yasuhiro Shimamoto
  • Publication number: 20140239381
    Abstract: An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 28, 2014
    Applicant: JTEKT CORPORATION
    Inventors: Satoshi TANNO, Yasuyuki WAKITA
  • Patent number: 8815686
    Abstract: A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Franz Hirler, Uwe Wahl, Thorsten Meyer, Michael Rüb, Armin Willmeroth, Markus Schmitt, Carolin Tolksdorf, Carsten Schaeffer
  • Patent number: 8772110
    Abstract: In a semiconductor device, a thin wall oxide film formed over sidewalls of an active region is formed, and a portion of the wall oxide film adjacent to a gate region is removed. A gate insulating film is formed where the portion of wall oxide film was removed to prevent a parasitic transistor from being generated by the wall oxide film.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seung Joo Baek
  • Patent number: 8765553
    Abstract: Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 1, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi Ying Liao
  • Patent number: 8754458
    Abstract: A solid-state imaging device includes an element forming region on the surface of a substrate, element isolating parts that isolate pixels, each of which is formed with a trench and a buried film, an opto-electric conversion element, and a buried-channel MOS transistor. The buried-channel MOS transistor includes a source region and a drain region, formed in the element forming region, that have a conductivity type opposite to that of the element forming region, a channel region having first and second impurity diffusion regions, which have a conductivity type opposite to that of the element forming region, and a gate electrode. Each first impurity diffusion region is formed between the source region and drain region on a side adjacent to one element isolating part. The second impurity diffusion region is formed across the region between the source region and drain region.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: June 17, 2014
    Assignee: Sony Corporation
    Inventor: Naoki Saka
  • Patent number: 8716764
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: May 6, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8692321
    Abstract: A semiconductor device includes a trench defined by etching a semiconductor substrate including a device isolation film and an active region, an active region protruded from a side and bottom of the trench, and a gate electrode surrounding the active region simultaneously while being buried in the trench.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 8, 2014
    Assignee: SK Hynix Inc.
    Inventor: Seong Wan Ryu
  • Patent number: 8674420
    Abstract: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hee Yeom
  • Patent number: 8653631
    Abstract: Provided are a transferred thin film transistor and a method of manufacturing the same. The method includes: forming a source region and a drain region that extend in a first direction in a first substrate and a channel region between the source region and the drain region; forming trenches that extend in a second direction in the first substrate to define an active layer between the trenches, the second direction intersecting the first direction; separating the active layer between the trenches from the first substrate by performing an anisotropic etching process on the first substrate inside the trenches; attaching the active layer on a second substrate; and forming a gate electrode in the first direction on the channel region of the active layer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 18, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, Jong-Hyun Ahn, Seung Youl Kang, Hasan Musarrat, In-Kyu You, Kyoung Ik Cho
  • Patent number: 8647949
    Abstract: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 11, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Michael Smith, Mark Helm, Kirk Prall
  • Patent number: 8643110
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Patent number: 8642430
    Abstract: Processes for preparing a stressed semiconductor wafer and processes for preparing devices including a stressed semiconductor wafer are provided herein. An exemplary process for preparing a stressed semiconductor wafer includes providing a semiconductor wafer of a first material having a first crystalline lattice constant. A stressed crystalline layer of a second material having a different lattice constant from the first material is pseudomorphically formed on a surface of the semiconductor wafer. A first via is etched through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer. The first via in the semiconductor wafer is filled with a first filler material to impede dissipation of stress in the semiconductor wafer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: February 4, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Stefan Flachowsky, Thilo Scheiper
  • Publication number: 20140014903
    Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.
    Type: Application
    Filed: August 21, 2013
    Publication date: January 16, 2014
    Inventor: Ravi Pillarisetty
  • Patent number: 8598627
    Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 3, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 8580597
    Abstract: A method for making a microelectronic device including, on a same substrate, at least one electro-mechanical component including a mobile structure of a monocrystalline semi-conductor material and a mechanism actuating and/or detecting the mobile structure, and with at least one transistor. The method a) provides a substrate including at least one first semi-conducting layer including at least one region in which a channel area of the transistor is provided, b) etches a second semi-conducting layer based on a given semi-conductor material, lying on an insulating layer placed on the first semi-conducting layer, to form at least one pattern of the mobile structure of the component in an area of monocrystalline semi-conductor material of the second semi-conducting layer, and at least one pattern of gate of the transistor on a gate dielectric area located facing the given region.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: November 12, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Eric Ollier, Audrey Berthelot