Abstract: Method of fabricating a lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: A MOSFET with low leakage current and method. The MOSFET has a substrate, a channel region, a source/drain region, a gate oxide layer and a conductive layer. The channel region in the substrate has a first region and a second region. The first region has a first threshold voltage and the second region has a second threshold voltage, respectively. The second region is located between the first region and the source/drain region. The first threshold voltage is smaller than the second threshold voltage. The leakage current of the MOSFET has an appropriate reduction by increasing the second threshold voltage of the second region. Significantly, by adjusting the size and position of the second region of the channel region, both the leakage current and the drain current of the MOSFET are readily optimized.

Abstract: A transistor fabrication method comprises: sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate; etching the substrate to form a trench; sequentially forming a first oxide film within the trench and a cylindrical insulation spacer at a lateral portion of the first oxide film; forming an insulation pattern; etching the silicon nitride film, the insulation pattern and the insulation spacer; removing the pad oxide film; removing the insulation spacer and the first oxide film; sequentially forming source/drain regions and LDD regions at both sides of the trench, under the remaining insulation pattern; forming a second oxide film; sequentially forming a channel stop layer between the LDD regions and a punch stop layer under the channel stop layer; and sequentially forming a gate insulation film and a gate region within the trench and the second oxide layer.

Abstract: The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract: A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Abstract: A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source and drain electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein: the gate recess width (Wri) and the gate length (LGo) are manufactured with predetermined respective values, in order that the access region, defined between the gate (G) and the gate recess edge (31), has an access region width (2&Dgr;o), derived from said predetermined values (Wri, LGo), which is sufficiently small to permit the transistor of functioning according to saturation current characteristics having continuous slopes.

Abstract: A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q11) are not directly connected to the drain of an MOS transistor (Q4) but are connected to the base of a bipolar transistor (Q12). The second field transistor (Q11) has its source connected to the collector of the bipolar transistor (Q12) and the MOS transistor (Q4) has its drain connected to the emitter of the bipolar transistor (Q12). When the current amplification factor of the bipolar transistor (Q12) is taken as &bgr;, then the current of the output (SO) can be increased approximately &bgr; times.

Abstract: A method of producing a SOI MOSFET which includes a fully depleted channel region of a first conductivity type formed in a top semiconductor layer disposed on an insulative substrate, source/drain regions of a second conductivity type formed to sandwich the channel region and a gate electrode formed on the channel region with intervention of a gate insulating film, the method comprises: forming the channel region by setting an impurity concentration of channel edge regions of the channel region adjacent to the source/drain regions higher than an impurity concentration of a channel central region of the channel region, and setting a threshold voltage Vth0 of the channel central region and a threshold voltage Vthedge of the channel edge regions so that a change of the threshold voltage Vth0 with respect to a change of the thickness of the top semiconductor layer and a change of the threshold voltage Vthedge with respect to the change of the thickness of the top semiconductor layer are of opposite sign.

Abstract: A metal-oxide-semiconductor protection transistor is formed in an active region of a semiconductor layer. The active region includes source and drain diffusion layers, which may be partly silicided, and a body region. A gate electrode extends across the active region above the body region. The breakdown voltage in the edge areas of the active regions is increased by increasing the gate length in the edge areas, by increasing the width of the active region below the gate electrode, or by increasing the non-silicided length of the source and drain diffusion layers in the edge areas. The edge areas of the active region are thereby protected from thermal damage during electrostatic discharges.

Abstract: Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.

Abstract: A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.

Abstract: A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer, etching a channel into the substrate through the groove, and depositing a cover layer over the masking layer and groove such that the covering layer at least substantially closes over the groove.

Abstract: A trench transistor formation method for creating source and drain regions and source and drain extension regions having an idealized doping profile using a single dopant implantation step. In one embodiment, the present invention is comprised of a method which includes forming a trench having sidewalls and a bottom into a substrate. The present embodiment also recites forming sidewalls spacer regions along at least a portion of the sidewalls of the trench. Subsequently, the present embodiment forms a gate dielectric along at least a portion of the bottom of the trench, and deposits a gate metal within the trench. The present embodiment then subjects the substrate to an etching process such that the top surface of the substrate is lower than the top surface of the sidewall spacer regions formed along the sidewalls of the trench.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: An impurity having a high electrical activation rate is introduced into a channel region, while an In implanted layer is formed in a very shallow region of the channel region. Impurities B, P are re-distributed such that their maximum impurity concentrations are reached at the same depth of a maximum impurity concentration in the In implanted layer, to form channel impurity regions which electrically act as impurities such as B, P, with a similar depth distribution to that of In. The resulting impurity distribution contributes both to the prevention of a punch-through phenomenon and to a large current driving capability of a highly miniaturized complementary MOS transistor.

Abstract: A buried channel and a method of fabricating a buried channel in a substrate including depositing a layer of masking material onto a surface of a substrate, etching a groove in the masking layer, etching a channel into the substrate through the groove, and depositing a cover layer over the masking layer and groove such that the covering layer at least substantially closes over the groove.

Abstract: A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel region is higher at an end portion of a surface depletion layer than at an interface between the semiconductor layer and the gate insulating film. The impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: The present invention provides a method for fabricating recessed lightly doped drain(LDD) field-effect transistors, comprising the steps of: providing a substrate and forming a sacrificial layer and a first dielectric layer on said substrate; patterning said sacrificial layer and said first dielectric layer so as to form a window; depositing a doped dielectric layer, wherein said doped dielectric layer is doped with dopants; etching back said doped dielectric layer so as to form spacers; forming a gate dielectric layer and lightly doped regions; depositing a conductor filling said window; removing said first dielectric layer; and heavily doping ions so as to form heavily doped regions. In this manner, a recessed lightly doped drain field-effect transistor is completed.

Abstract: A high voltage MOS device (100) is disclosed. The MOS device comprises an n-well region (113) with a top layer (108) of opposite conductivity. A thin layer of oxide (124) is formed over the top layer (108).

Abstract: A buried-channel PMOS device is fabricated simultaneously with a surface-channel device if the gate is doped N-type while the NMOS gates are doped and the P+ source/drain doping is blocked from the “high” P-channel device. In the normal process the “high” PMOS is not fully self-aligned. However, when the PMOS process includes a lightly-doped drain (PLDD), the LDD doping is self-aligned.

Abstract: A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region.

Abstract: A method of manufacturing a semiconductor integrated circuit device comprises forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a polycrystal silicon film on the gate insulating film, etching the polycrystal silicon film to form a gate electrode on a portion of the gate insulating film, etching the gate insulating film except at the portion thereof where the gate electrode has been formed, and forming a thermal oxide film on the semiconductor substrate at regions corresponding to the etched gate insulating film. Impurities of a second conductivity type are implanted into a source region in the semiconductor substrate through the thermal oxide film to form a body region of the second conductivity type. The semiconductor substrate is then heated at a temperature of 1000° C. or higher.

Abstract: A process having a robust process sequence for producing an MOS field effect transistor having a horizontal buried gate formed of polysilicon and a recombination zone provided at the surface of the transistor includes the steps of producing the horizontal polysilicon gate first and then introducing the recombination zone. The process allows producing a transistor without encountering problems caused by the insufficient high-temperature compatibility of metals.

Abstract: In a region on the left hand of FIG. 1 with respect to the gate electrode (107), a first source region (103a), a body-potential drawing region (105) and a second source region (103b) are formed in this order along the vertical direction of this figure. The first and second source regions (103a, 103b) are of n+ type, and the body-potential drawing region (105) is of p+ type. In a thin-film transistor (100), the body-potential drawing region (105) can draw and fix a body potential.

Abstract: A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: A field effect transistor having a high breakdown withstand capacity is provided. An active region 7a is surrounded by a fixed potential diffusion layer 16, and a channel region 15 is formed in the active region 7a. A gate pad 35 is provided outside the fixed potential diffusion layer 16. Minority carriers injected at a peripheral region of the active region 7a flow into the fixed potential diffusion layer 16, which prevents breakdown attributable to concentration of the carriers. The fixed potential diffusion layer 16 is surrounded by a plurality of guard ring diffusion layers 171 through 174, and a pad diffusion layer 18 formed in a position under the gate pad 35 is connected to the innermost guard ring diffusion layer 171. Since this encourages expansion of a depletion layer under the gate pad 35, an increased breakdown voltage is provided.

Abstract: A semiconductor storage unit and a method of manufacturing the same are provided. In the semiconductor storage unit, the formation of a gate electrode within a semiconductor substrate decreases the occurrence of a short circuit between conductive layers, provides an excellent electric connection in a connection hole between the semiconductor substrate and a conductive layers, and also reduces the number of manufacturing processes. In a semiconductor substrate, unit memory cells and are formed by providing a gate electrode in a region where a second opening is formed in a first opening, a first impurity-diffusion layer, a second impurity-diffusion layer, a third impurity-diffusion layer, a bit line, a charge-storage electrode, a capacity insulating film, and a plate electrode. Regions where the second opening is not formed are isolation regions and between memory cells.

Abstract: The present invention is a method for fabricating a semiconductor device having an elevated source/drain scheme which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film on the first photoresist film; forming the second photoresist film; forming a second photoresist film pattern so that a portion corresponding to a field region has a first opening and a region in which a gate electrode is to be formed has a second opening by exposing the second photoresist film to a first light, thereby developing the second photoresist film; forming a first photoresist film pattern so that a portion corresponding to the field region has a third opening by exposing the first photoresist film to a second light, thereby developing the first photoresist film; forming a first trench at the first opening position and a second trench at the second opening position on the semiconductor substrate by etching the semiconductor substrate using the first

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: A power semiconductor device having an improved high breakdown voltage and improved productivity, and a fabrication method thereof are provided. The power semiconductor includes a collector region of a first conductivity type formed in a semiconductor substrate, a base region of second conductivity type formed in the collector region, and an emitter region of the first conductivity type formed in the base region. A channel stop region is formed being spaced a predetermined distance from the base region. An insulative film, a semi-insulating polycrystalline silicon (SIPOS) film, and a nitride film patterned respectively to expose the emitter region, the base region, and the channel stop region are sequentially deposited on the semiconductor substrate. A base electrode, an emitter electrode, and an equipotential electrode connected respectively to the base region, the emitter region, and the channel stop region are formed.

Abstract: A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

Abstract: An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.

Abstract: A novel high-speed, highly reliable VSLI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.

Abstract: A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the Vcc and Vss. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for highperformance, low-voltage, and low-power VLSI circuits on SOI wafers.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850° C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850° C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850° C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850° C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: In a field effect transistor, an element isolation trench is formed around the element region on the major surface of a silicon substrate. A gate electrode is formed on the major surface in the element region via a gate insulating film. Source and drain regions are formed on the major surface of the element region to oppose via a channel region under the gate electrode. The channel region has a main portion having an upper surface at a level higher than the upper end portion of a trench side wall, and a side portion having an upper surface tilting downward from the main portion to the upper end portion of the trench side wall. The dopant impurity in the channel region has a concentration peak located at a level lower than the upper end portion of the trench side wall. The distance from the upper surface of the main portion to the concentration peak is larger than that from the upper surface of the side portion to the peak.

Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.

Abstract: A semiconductor device with improved short channel characteristics is formed with a buried amorphous region comprising a retrograde impurity region having the impurity concentration peak of the semiconductor substrate. The buried amorphous region, formed below the channel region, suppresses diffusion of displaced atoms and holes from the source/drain regions and reduces the resistance against latch-up phenomenon, thereby improving short channel characteristics.

Abstract: A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

Abstract: A method of fabricating an SOIMOS transistor, isolated by trench isolation, which can prevent a gate oxide film from dielectric breakdown on peripheral edge portions of an SOI layer while preventing formation of parasitic MOS transistors on the peripheral edge portions of the SOI layer under a gate electrode is provided. A nitride film (6) is removed with phosphoric acid of about 160° C. in temperature and thereafter a polysilicon film (5) is removed by isotropic dry etching, thereby leaving a pad oxide film (4) and side wall oxide films (7) in a state enclosed with a deposition oxide film (8). Thereafter the pad oxide film (4), the side wall oxide films (7) and the deposition oxide film (8) are simultaneously removed with hydrofluoric acid.