Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.

Abstract: A method for making a microelectronic device including, on a same substrate, at least one electro-mechanical component including a mobile structure of a monocrystalline semi-conductor material and a mechanism actuating and/or detecting the mobile structure, and with at least one transistor. The method a) provides a substrate including at least one first semi-conducting layer including at least one region in which a channel area of the transistor is provided, b) etches a second semi-conducting layer based on a given semi-conductor material, lying on an insulating layer placed on the first semi-conducting layer, to form at least one pattern of the mobile structure of the component in an area of monocrystalline semi-conductor material of the second semi-conducting layer, and at least one pattern of gate of the transistor on a gate dielectric area located facing the given region.

Abstract: One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method comprises forming a first silicon film on a semiconductor substrate, forming a second silicon film on the first silicon film, forming a third silicon film on the second silicon film, and forming a first diffusion barrier film on the third silicon film. The method further comprises performing a thermal treatment to diffuse an impurity included in the second silicon film into at least the first silicon film and the semiconductor substrate, respectively.

Abstract: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: A method for manufacturing components on a mixed substrate. The method comprises the following steps: providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, forming in this substrate a plurality of trenches opening out at a free surface of the thin layer and extending over a depth such that each trench passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.

Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.

Abstract: A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.

Abstract: A process for manufacturing a semiconductor device, in which a current flows in a deflected part that includes a semiconductor, includes forming a straight beam having a doubly-clamped beam structure that includes the semiconductor by forming a void under the beam, filling the void with a liquid, and contacting a center of the beam with a bottom of the void by drying the liquid to form the deflected part.

Abstract: A method for forming strained epitaxial carbon-doped silicon (Si) films, for example as raised source and drain regions for electronic devices. The method includes providing a structure having an epitaxial Si surface and a patterned film, non-selectively depositing a carbon-doped Si film onto the structure, the carbon-doped Si film containing an epitaxial carbon-doped Si film deposited onto the epitaxial Si surface and a non-epitaxial carbon-doped Si film deposited onto the patterned film, and non-selectively depositing a Si film on the carbon-doped Si film, the Si film containing an epitaxial Si film deposited onto the epitaxial carbon-doped Si film and a non-epitaxial Si film deposited onto the non-epitaxial carbon-doped Si film. The method further includes dry etching away the non-epitaxial Si film, the non-epitaxial carbon-doped Si film, and less than the entire epitaxial Si film to form a strained epitaxial carbon-doped Si film on the epitaxial Si surface.

Abstract: A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain.

Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).

Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.

Abstract: A solid-state imaging device includes an element forming region formed on the surface of a substrate, element isolating parts that isolate pixels formed on the substrate, each of which is formed with a trench and a buried film, an opto-electric conversion element, and a buried-channel MOS transistor. The buried-channel MOS transistor includes a source region and a drain region, formed in the element forming region, that have a conductivity type opposite to that of the element forming region, a channel region having first impurity diffusion regions and a second impurity diffusion region, which have a conductivity type opposite to that of the element forming region, and a gate electrode. Each first impurity diffusion region is formed between the source region and drain region on a side adjacent to one element isolating part. The second impurity diffusion region is formed across the region between the source region and drain region.

Abstract: A semiconductor device having a saddle fin gate and a method for manufacturing the same are presented. The semiconductor device includes a semiconductor substrate, an isolation structure, and gates. The semiconductor substrate is defined with first grooves in gate forming areas. The isolation structure is formed in the semiconductor substrate and is defined with second grooves which expose front and rear surfaces of the gate forming areas. The gates are formed within the first grooves in the gate forming areas. Gates are also formed in the second grooves of the isolation structure to cover the exposed front and rear surfaces of the gate forming areas. The second grooves are wider at the lower portions that at the upper portions.

Abstract: A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material having a top surface recessed to reduce overlap capacitance with respect to the source and drain diffusion regions formed at an upper substrate surface at either side of the gate electrode. There is optionally formed halo implants at either side of and abutting the gate electrode, each halo implants extending below the source and drain diffusions into the channel region. Additionally, highly doped source and drain extension regions are formed that provide a low resistance path from the source and drain diffusion regions to the channel region.

Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: A high-voltage junction field-effect transistor (JFET) includes a semiconductor substrate, a well region, first, second, and third doped regions, and first, second, and third terminals. The first doped region is disposed in the well region and the second dope region is laterally displaced from the well region. The third doped region is disposed in the well region between the first and second doped regions. A portion of the well region is substantially depleted of free charge carriers when a first voltage between the first and second terminals is greater than or equal to a pinch-off voltage. A voltage output at the third terminal is substantially proportional to the first voltage when the first voltage is less than the pinch-off voltage, and the voltage output at the third terminal is substantially fixed and less than the first voltage when the first voltage is greater than or equal to the pinch-off voltage.

Abstract: A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased.

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract: A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

Abstract: A manufacturing method of a thin film transistor having at least a gate electrode, a gate insulation film, an oxide semiconductor layer, a first insulation film, a source electrode, a drain electrode, and a second insulation film on a substrate, including: forming the gate electrode on the substrate; forming the gate insulation film on the gate electrode; forming a semiconductor layer including amorphous oxide on the gate insulation film; patterning the gate insulation film; patterning the oxide semiconductor layer; reducing the oxide semiconductor layer in resistance by forming the first insulation film on the oxide semiconductor layer in the atmosphere not including an oxidized gas; patterning the first insulation film and forming a contact hole between the source electrode and the drain electrode and the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer in the oxide semiconductor layer through the contact hole; forming the source electrode and the drain electrode throu

Abstract: A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, the method including providing a semiconductor body having a first and a second side and a basic doping of a first conduction type. The method further includes irradiating the semiconductor body via one of the sides with protons, as a result of which protons are introduced into a first region of the semiconductor body situated at a distance from the irradiation side. The method also includes carrying out a thermal process in which the semiconductor body is heated to a predetermined temperature for a predetermined time duration, the temperature and the duration being chosen such that hydrogen-induced donors are generated both in the first region and in a second region adjacent to the first region in the direction of the irradiation side.

Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device may include a source, a drain, a gate positioned proximate to the source, a drift region disposed substantially between the drain and a region of the gate and the source, and a self shielding region disposed proximate to the drain. A corresponding method is also provided.

Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.

Abstract: A pressure sensor includes a sense element port, a support ring and a plurality of interference fit slits to provide a flexible interference fit between the sense element port and the support ring to form a substantially flush lap joint. The sensor also includes an electronics board inside the support ring and attached to planar mounting tabs which provide a stable mounting. Gel flow barriers protect electronics board features from unwanted non-conductive gel. Double-ended symmetrical, tapered contact springs provide manufacturing cost savings and contribute to improved alignment of an interface connector of the sensor.

Abstract: A semiconductor device includes a semiconductor substrate having an active region having a plurality of recessed channel areas extending across the active region and a plurality of junction areas also extending across the active region. Gates are formed in and over the recessed channel areas of the active region. A device isolation structure is formed in the semiconductor substrate to delimit the active region, and the device isolation structure has recessed portions, each of which is formed near a junction area of the active region. Landing plugs are formed over each junction area in the active region and extend to fill the recessed portion of the device isolation structure outside the active region. The semiconductor device suppresses interference caused by an adjoining gate leading to a decrease in leakage current from a cell transistor.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.

Abstract: To provide a manufacturing method of a MOS field-effect transistor in which such a structure is adopted that SiGe having a large lattice constant is embedded immediately below a channel and distortion is effectively introduced in a channel Si layer so that mobility of electrons or holes are drastically improved, thereby realizing high-speed operation and low power consumption. A stressor 2 composed of silicon germanium is formed in a portion in an active region that is separated by an insulating film formed on a silicon substrate, a silicon channel layer 1 composed of silicon is formed above the stressor, and a tensile stress layer 10 is formed so as to surround a gate electrode and a sidewall formed on the gate electrode.

Abstract: Provided is a semiconductor device which includes a metal oxide semiconductor (MOS) transistor having high driving performance and high withstanding voltage with a thick gate oxide film. In the local oxidation-of-silicon (LOCOS) offset MOS transistor having high withstanding voltage, in order to prevent a gate oxide film (6) formed on a channel formation region (7) from being etched at a time of removing the gate oxide film (6) with a polycrystalline silicon gate electrode (8) being used as a mask to form a second conductivity type high concentration source region (4) and a second conductivity type high concentration drain region (5), a source field oxide film (14) is formed also on a source side of the channel formation region (7), and in addition, a length of a second conductivity type high concentration source field region (13) is optimized. Accordingly, it is possible to obtain a MOS transistor having high driving performance and high withstanding voltage with a thick gate oxide film.

Abstract: There is provided a semiconductor device having a switching element, including a first semiconductor layer including a first, second and third surfaces, a first electrode connected to the first semiconductor layer, a plurality of second semiconductor layers selectively configured on the first surface, a third semiconductor layer configured on the second semiconductor layer, a second electrode configured to be contacted with the second semiconductor layer and the third semiconductor layer, a gate electrode formed over the first semiconductor layer, a first region including a first tale region, a density distribution of crystalline defects being gradually increased therein, a peak region crossing a current path applying to a forward direction in a p-n junction, a second tale region continued from the peak region, and a second region including a third tale region, the density distribution of the crystalline defects being gradually increased therein.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a transistor structure including a gate electrode and a first channel region and source/drain regions on a substrate, and a second channel region and source/drain regions provided on the transistor structure. Accordingly, transistor operations can utilize the current path above and below the gate electrode.

Abstract: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminium is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminium to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.

Abstract: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer.

Abstract: A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

Abstract: An embodiment of the present invention relates to a semiconductor device having a multi-channel and a method of fabricating the same. In an aspect, the semiconductor device includes a semiconductor substrate in which isolation layers are formed, a plurality of trenches formed within an active region of the semiconductor substrate, and a channel active region configured to connect opposite sidewalls within each trench region and having a surface used as a channel region.

Abstract: A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.

Abstract: Devices comprising, and a method for fabricating, a remote doped high performance transistor having improved subthreshold characteristics are disclosed. In one embodiment a field-effect transistor includes a channel layer configured to convey between from a source portion and a drain portion of the transistor when the transistor is in an active state. Further, the field-effect transistor includes a barrier layer adjacent to the channel layer. The barrier layer comprises a delta doped layer configured to provide carriers to the channel layer of the transistor, while preferably substantially retaining dopants in said delta-doped layer.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract: A multilayer embedded stressor having a graded dopant profile for use in a semiconductor structure for inducing strain on a device channel region is provided. The inventive multilayer stressor is formed within areas of a semiconductor structure in which source/drain regions are typically located. The inventive multilayer stressor includes a first conformal epi semiconductor layer that is undoped or lightly doped and a second epi semiconductor layer that is highly dopant relative to the first epi semiconductor layer. The first and second epi semiconductor layers each have the same lattice constant, which is different from that of the substrate they are embedded in. The structure including the inventive multilayer embedded stressor achieves a good balance between stress proximity and short channel effects, and even eliminates or substantially reduces any possible defects that are typically generated during formation of the deep source/drain regions.

Abstract: A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.