Abstract: The method includes patterning a first polysilicon layer on a substrate. A first dielectric having a first via hole is defined over the substrate. A second polysilicon layer is formed along the surface of the first dielectric layer and refilled into the first via hole. Then, an etching is used to etch the layer. A residual portion of the layer is located at the lower portion of the first via hole. An undoped polysilicon is then patterned on the first dielectric layer and along the surface of the first via hole. An isolation structure is then refilled into the first via hole. An oxide layer is formed on the first polysilicon, the first dielectric layer and the upper surface of isolation structure to act as the gate oxide of the TFT. Then, the oxide and the first dielectric layer are etched to define a second via hole. A further polysilicon layer is pattern on the first dielectric layer and refilled into the second via hole for defining the gate.

Abstract: A field effect transistor (FET) with a V-shaped trench gate in a semiconductor substrate having gate oxide on the walls of the trench and a gate electrode material within the trench walls, and source/drain impurities in the semiconductor substrate and abutting the gate oxide. The resultant FET structure comprises a non-self align V-shaped gate with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Because of the V-shaped structure of the gate, the effective length of the channel only extends from the edge of the source to the tip of the V-shaped gate. Due to this characteristic, the width of the gate at the surface of the semiconductor substrate can be two or more time the distance of the desired channel length thereby permitting conventional lithography to be used to fabricate gate lengths much shorter than the lithography limit. Preferably, the bottom or tip of the V shaped gate is rounded and concave.

Abstract: The method of forming buried contacts on a semiconductor substrate is as follows. At first, a gate insulator layer is formed on the substrate. An undoped silicon layer is then formed on the substrate, and a dielectric layer is formed on the undoped silicon layer. Portions of the dielectric layer, of the undoped silicon layer, and of the gate insulator layer are removed to define a buried contact opening. A doping step is carried out to dope the substrate for forming a buried contact region. A doped silicon layer is formed over the substrate. Next, a portion of the doped silicon layer is then removed to leave a silicon connection and a doped silicon sidewall. The dielectric layer is removed and a thermal oxidization is performed to form a thermal oxide layer on the exposed silicon surfaces. A gate region is defined by removing portions of the thermal oxide layer and the undoped silicon layer. The substrate is doped for forming a lightly doped source/drain region.

Abstract: A method to form buried channel MOSFETs in an integrated circuit is described. Field oxide isolation regions overlying a semiconductor substrate are provided. The surface of the substrate in the active device regions is cleaned. A doped silicate glass layer overlying the field oxide regions and the substrate is deposited and etched to remove the silicate glass layers in all areas except where counter-doped junctions of the buried channel MOSFETs are planned. The substrate and the doped silicate glass are annealed to diffuse ions from the doped silicate glass into the substrate and to form the counter-doped junctions. The silicate glass is etched away. The surface of the substrate is cleaned in the active device regions. A gate oxide layer is deposited. A doped polysilicon layer is deposited and etched to form gates for the MOSFETs overlying the counter-doped junctions. Sidewall spacers are formed.

Abstract: A CMOS logic gate for a semiconductor apparatus having a buried channel NMOS transistor and a fabrication method of the same are disclosed. The CMOS logic gate according to the present invention includes a pull up unit gate-connected by an input voltage and pulling up an output voltage, a buried channel NMOS transistor connected with the pull up unit and gate-connected by a power voltage, and a surface channel NMOS transistor connected with the buried channel NMOS transistor and gate-connected by the input voltage for pulling down the output voltage for thereby enhancing a reliability of the CMOS logic gate.

Abstract: The invention comprises a transistor having a self-aligned implant under the gate. The transistor comprises a drain region, a source region opposite the drain region, and a channel region in a semiconductor substrate extending between the source region and the drain region. A front gate is disposed outwardly from the first substrate layer and is separated from the channel region by a dielectric layer. The front gate comprises a first gate layer disposed outwardly from the dielectric layer and a second gate layer disposed outwardly from the first gate layer. A self-aligned implant region is disposed inwardly from the channel region and in approximate vertical alignment with the front gate.

Abstract: Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure. Both sides of each gate are oxidized thus preventing possible shorts between source and gate regions and between drain and gate regions. The top of each gate is silicided once the protective layer of silicon nitride is removed.

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Abstract: A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

Abstract: A method for manufacturing a buried-channel pMOSFET device that utilizes a plasma doping technique to form a very shallow P-type channel layer on the top surface of a sub-micron buried-channel pMOSFET. The buried-channel pMOSFET device formed by the method has a higher current drivability and a higher anti-punchthrough resistance.

Abstract: A method for manufacturing a power semiconductor device including a semi-insulating polycrystalline silicon (SIPOS) film is provided. According to this method, first, a conductive collector region is formed in a semiconductor substrate. Then, a first insulating film, which exposes a portion of the semiconductor substrate in which a base region is to be formed, is formed on said semiconductor substrate in which the collector region is formed. A conductive base region is formed in the collector region. A second insulating film is formed over the entire surface of the semiconductor substrate. After exposing a portion of the semiconductor substrate in which an emitter region and a channel stop region are to be formed, impurities for the emitter region are implanted into the base region. Simultaneously, a third insulating film is formed over the entire surface of the semiconductor substrate, while a conductive emitter region is formed by diffusing the impurities.

Abstract: A method for fabricating a high-voltage device substrate comprising the steps of forming a pad oxide layer and a mask layer over a substrate. Then, the pad oxide layer and the mask layer are patterned to define a region for a first ion implantation. Next, the exposed substrate is oxidized to form a field oxide layer. Thereafter, the mask layer is removed followed by a first ion implantation. Next, a portion of the field oxide layer is removed, and then a second ion implantation is performed implanting ions into the exposed substrate. Then, a conformal oxide layer is formed over the substrate surface. Next, a high temperature drive-in and oxidation operation is carried out, in which ions in the first ion implanted region and the second ion implanted region are driven deeper into the substrate interior, and at the same time the substrate above those regions are oxidized. Finally, the oxide layer on the substrate surface is removed, and then an epitaxial layer is formed over the substrate.

Abstract: A mask ROM uses a bit line structure having a vertically graded dopant distribution or a distinct two level dopant distribution. A bit line might include a highly doped region buried deeply within the substrate that is connected to a comparatively lightly doped region formed above the more highly doped region. The vertical structure of the bit line allows the bit line to be less resistive than the simpler shallow bit line structure conventionally used. The vertical structure (i.e., the two level or graded structure) of the bit line allows the bit line to have a lower doping immediately adjacent the channel region, which reduces the likelihood of punchthrough. The deeper, highly doped portions of the bit line are narrow and laterally confined so that well defined antipunchthrough implantations can be formed which lie between but separated from the more highly doped portions of the bit lines.

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact.

Abstract: A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface.

Abstract: A process of fabricating a semiconductor device, includes the steps of: forming a side wall insulating film on a side portion of a gate electrode formed on a silicon substrate; forming a source/drain region in the silicon substrate, and subjecting the source/drain region to an activating heat treatment; forming a metal film on the surface of the source/drain region, and making the metal film react with the silicon substrate by a heat treatment thereby forming a silicide layer; wherein a first furnace heat treatment is performed after formation of the side wall insulating film and before formation the source/drain region; and an oxide film formed on the surface of the silicon substrate is removed before formation of the metal film, a surface side of the silicon substrate is made amorphous by doping ions of arsenic into the silicon substrate, and the metal film is formed.

Abstract: A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom surface of the trench between the spacers, forming a gate electrode on the gate insulator and the spacers, removing at least portions of the spacers to form voids in the trench after forming the gate electrode, implanting localized source and drain regions through the voids and through the bottom surface of the trench outside the gate electrode, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the dopant concentration of the localized source and drain regions is controlled by the amount of the spacers, if any, left intact when the localized source and drain regions are implanted after removing the portions of the spacers.

Abstract: A method of forming an IGFET includes forming a trench with opposing sidewalls and a bottom surface in a substrate, selectively growing an oxide layer on the bottom surface so that the oxide layer includes a thick region between thin regions, implanting localized source and drain regions through the thin regions using the thick region as an implant mask, stripping the oxide layer, forming a gate insulator and gate electrode in the trench, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the locations and dopant concentrations of the localized source and drain regions are controlled by the dimensions of the selectively grown oxide layer.

Abstract: A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer.

Abstract: A NAND-structure and amorphous-silicon based ROM device is provided. This ROM device is of the type including an array of MOSFET memory cells that are constructed based on a silicon-on-insulator (SOI) structure, so as to isolate the source/drain regions from the underlying substrate to prevent the occurrence of leakage current therebetween. Further, the SOI structure prevents occurrence of breakdown at the diode junction between the source/drain regions and the substrate for increased operating voltage. In this ROM device, the source/drain regions for the MOSFET memory cells are formed from the intrinsic amorphous-silicon, instead of highly-doped polysilicon, so that the fabrication process for the ROM device is significantly simplified.

Abstract: A new semiconductor structure for a ROM device and a method for fabricating the same are provided. The ROM device includes a plurality of trench-type source/drain regions which serve as a plurality of bit lines for the ROM device. By this method, the conventional step of using ion implantation to form the bit lines can be eliminated. Further, an insulating layer is formed between the source/drain regions and the underlying substrate such that the leakage current in the junction between the source/drain regions and the substrate can be minimized. The ON/OFF state of each of the MOSFET memory cells of the ROM device is dependent on whether the associated channel region comes into lateral contact with the neighboring source/drain regions through a mask removed portion of the insulating layer.

Abstract: A method for fabricating a semiconductor device having a buried channel structure, in which impurities having the same conductive type as a well are ion implanted, to increase the ion density beneath the buried channel, thereby enhancing the short channel characteristic and smooth on/off characteristic of MOSFET.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: A ROM device using a Shockly diode uses the Shockly diode as a memory cell in the ROM device. In the present invention, the current of the memory cell is larger than that of a convention one. In the conventional ROM device, the code is programmed by making use of the channel transistor as the memory cell and implanting. In the present invention, the code is programmed by defining contact windows of the ROM device to prevent the ROM device from the shortcomings of limited current. In addition, the memory cells of the ROM device of a Shockly diode are isolated by an insulating layer, resulting in a smaller area for the device and improved integrity.

Abstract: A structure and manufacturing method for ROM suitable for high density component fabrication, mainly consisting of conducting diode memory cells having a forward bias voltage of about 0.4V located above a silicon substrate, and of non-conducting memory cells having only the bit lines embedded in the substrate, forming a memory unit for the storage and retrieval of data bits at the junction crossing between each word line and each bit line. When a suitable operating voltage is applied to a word line, a change of current flow detected in the selected bit line represents either the ON or OFF state of a memory unit and hence reflects the coded data bit.

Abstract: A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

Abstract: A method of forming a multi-stage ROM which replaces the multiple code implant. A gate oxide layer, a first polysilicon layer, an oxide layer, a second polysilicon layer and a silicon nitride layer are formed over a substrate in succession. Then, the silicon nitride layer, the second polysilicon layer, the oxide layer, the first polysilicon layer and the gate oxide layer are patterned at the same time so that a number of double-layer polysilicon lines remain. An implantation is performed on an exposed region to form a number of source/drain regions which serve as bit lines. The double-layer polysilicon lines are patterned to form a number of gates, wherein each of the gates combines with the adjacent source/drain regions to form four memory cells. Two coding processes are performed to accomplish the process of manufacturing a multi-stage ROM.

Abstract: A method of making multi-level ROM devices in which the gate width controls the threshold voltage setting of each memory unit, instead of the conventional method of setting the threshold voltage through the implantation of ions into the channel region of a memory unit. The memory units include memory units having their word line polysilicon layer completely removed, which are units in an OFF state. Memory units having part of the word line polysilicon layer removed are units with a higher threshold voltage, while memory units having the word line polysilicon layer left untouched are memory units with a lower threshold voltage.

Abstract: There is disclosed a short-channel FET which is excellent in properties and adapted for mass production. FETs of this construction can be packed at a high density. There is also disclosed a method for forming this FET. The semiconductor substrate of this FET has a plateau-shaped portion protruding from the body of the substrate. This plateau-shaped portion is substantially identical in contour with a gate electrode formed over it. The gate electrode is in register with the plateau-shaped portion. With respect to the relation of doped regions of the substrate becoming the source and drain to the channel region, the narrowest portion in the channel region is not in contact with a gate-insulating film.

Abstract: A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

Abstract: A process for fabricating an MOS device (44) having a segmented channel region (48) includes the fabrication of a compound MOS gate electrode (46). Both the segmented channel region (48) and the MOS gate electrode (46) are formed by creating an opening (18) and an insulating layer (16) overlying a first polycrystalline silicon layer (14). The lateral extent of both the MOS gate electrode (46) and a buried junction region (24) formed in the semiconductor substrate (10) are defined by first sidewall spacer (22) and a second sidewall spacer (32) formed adjacent to the first sidewall spacer (22).

Abstract: A memory cell, and process for making it, having a long channel and narrow buried bit line is disclosed. The memory cell is formed in a substrate having a first dopant type. A trench is defined in the substrate. Source/drain regions of a second dopant type are formed on the surface of the substrate to each side of the trench. A gate oxide layer is formed over the substrate and a polysilicon wordline deposited over the gate oxide layer. A channel is defined along the walls of the trench. Ions are implanted in the bottom of the trench defining the channel for a cell that is selected to be in the off state. The long channel and narrow bit line of these memory cells overcome the problem of high bit line resistance and low junction breakdown voltage found in conventional memory cells.