Closed Or Loop Gate Patents (Class 438/284)
  • Patent number: 10515962
    Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
  • Patent number: 10229975
    Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • Patent number: 9871102
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee
  • Patent number: 9802815
    Abstract: A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 31, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Michael Julian Daneman, Mei-Lin Chan, Martin Lim, Fariboz Assaderaghi, Erhan Polatkan Ata
  • Patent number: 9799736
    Abstract: A gallium-doped sacrificial epitaxial or polycrystalline germanium layer is formed on a silicon germanium substrate having a high percentage of germanium followed by annealing to diffuse the gallium into the silicon germanium substrate. The germanium layer is selectively removed to expose the surface of a gallium-doped silicon germanium region within the silicon germanium substrate. The process has application to the formation of electrically conductive regions within integrated circuits such as source/drain regions and junctions without the introduction of carbon into such regions.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mona Abdulkhaleg Ebrish, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9716090
    Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
  • Patent number: 9064786
    Abstract: Various embodiments include dual three-dimensional (3D) resistor structures and methods of forming such structures. In some embodiments, a dual 3D resistor structure includes: a dielectric layer having a first set of trenches extending in a first direction through the dielectric layer; and a second set of trenches overlayed on the first set of trenches, the second set of trenches extending in a second direction through the dielectric layer, the second set of trenches and the first set of trenches forming at least one dual 3D trench; and a resistor material overlying the dielectric layer and at least partially filling the at least one dual 3D trench along the first direction and the second direction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Patent number: 9035379
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
  • Patent number: 9029211
    Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 12, 2015
    Assignee: Semicoductor Manufacturing International (Shanghai) Corporation
    Inventor: Deyuan Xiao
  • Patent number: 9018055
    Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthew T. Currie
  • Patent number: 9012284
    Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
  • Patent number: 8999779
    Abstract: A low resistance contact to a finFET source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finFET can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain. Facing growth fronts can merge or can form unmerged facets. A dielectric material can fill voids within the source drain region. A trench spaced from the finFET gate can expose the top portion of faceted epitaxial growth on fins within said trench, such top portions separated by a smooth dielectric surface. A silicon layer selectively formed on the top portions exposed within the trench can be converted to a semiconductor-metal layer, connecting such contact with individual fins in the source drain region.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Naczas, Vamsi Paruchuri, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 8952392
    Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Yi-Po Lin, Jiunn-Hsiung Liao, Shui-Yen Lu, Li-Chiang Chen
  • Patent number: 8951870
    Abstract: Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Bruce Doris, Ali Khakifirooz, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150021715
    Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Gen P. Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8937359
    Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: January 20, 2015
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Shom Ponoth, David V. Horak, Balasubramanian Pranatharthiharan
  • Patent number: 8933483
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Patent number: 8933518
    Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
  • Publication number: 20140353574
    Abstract: A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2?n?20. The channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 4, 2014
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Yi Song
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8890243
    Abstract: In the interior of a semiconductor substrate having a main surface, a first p? epitaxial region is formed, a second p? epitaxial region is formed on the main surface side, and an n-type drift region and a p-type body region are formed on the main surface side. An n+ buried region is formed between the first p? epitaxial region and the second p? epitaxial region in order to electrically isolate the regions. A p+ buried region having a p-type impurity concentration higher than that of the second p? epitaxial region is formed between the n+ buried region and the second p? epitaxial region. The p+ buried region is located at least immediately under the junction between the n-type drift region and the p-type body region so as to avoid a site immediately under a drain region which is in contact with the n-type drift region.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Shinichiro Yanagi
  • Patent number: 8871576
    Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao
  • Patent number: 8871584
    Abstract: A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 28, 2014
    Assignee: Advanced Ion Beam Technology, Inc.
    Inventors: Daniel Tang, Tzu-Shih Yen
  • Publication number: 20140312432
    Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 23, 2014
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 8865553
    Abstract: A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 21, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventors: Wolfgang Einbrodt, Daniel Gaebler
  • Patent number: 8859363
    Abstract: Methods of fabricating semiconductor devices may include forming first trenches in a substrate to define fin patterns and forming buried dielectric patterns filling lower regions of the first trenches. The first trenches extend in parallel. A gate dielectric layer is formed on upper inner sidewalls of the first trenches, and a gate conductive layer filling the first trenches is formed on the substrate including the gate dielectric layer. The gate conductive layer, the gate dielectric layer and the fin patterns are patterned to form second trenches crossing the first trenches and defining active pillars. Semiconductor devices may also be provided.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeik Kim, HyeongSun Hong, Yongchul Oh, Yoosang Hwang
  • Publication number: 20140291772
    Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
    Type: Application
    Filed: June 10, 2014
    Publication date: October 2, 2014
    Inventors: Willy RACHMADY, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
  • Patent number: 8846477
    Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu Cai, Ruilong Xie
  • Patent number: 8835239
    Abstract: Various aspects of the technology include a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: September 16, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8828819
    Abstract: Performance of P-channel transistors may be enhanced on the basis of an embedded strain-inducing semiconductor alloy by forming a gate electrode structure on the basis of a high-k dielectric material in combination with a metal-containing cap layer in order to obtain an undercut configuration of the gate electrode structure. Consequently, the strain-inducing semiconductor alloy may be formed on the basis of a sidewall spacer of minimum thickness in order to position the strain-inducing semiconductor material closer to a central area of the channel region.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephen Kronholz, Markus Lenski, Vassilios Papageorgiou
  • Patent number: 8815691
    Abstract: The device includes a wafer substrate including an isolation feature, a fin base embedded in the isolation feature, at least one channel disposed above the fin base, and a gate stack disposed around the channel, wherein the gate stack includes a top portion and a bottom portion of the gate stack formed by filling a cavity around the channel such that the top portion and bottom portion are aligned each other. The device further includes at least one source and one drain disposed over the fin base, wherein the channel connects the source and the drain. The device further includes the source and the drain disposed over a fin insulator disposed over the fin base.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 8809178
    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 19, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Michael Hargrove, Xiaodong Yang, Hans van Meer, Laegu Kang, Christian Gruensfelder, Srikanth Samavedam
  • Publication number: 20140227849
    Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Nicholas V. LiCausi, Jeremy A. Wahl
  • Patent number: 8803231
    Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 12, 2014
    Assignee: Seiko Instruments, Inc.
    Inventors: Tomomitsu Risaki, Jun Osanai
  • Patent number: 8803232
    Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ker Hsiao Huo, Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng
  • Patent number: 8779524
    Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5s.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Yoshiya Moriyama, Hiromasa Fujimoto, Satoru Itou, Susumu Akamatsu, Hiroshi Ohkawa
  • Patent number: 8772099
    Abstract: A method of detecting a detection target using a sensor requires a sensor having a transistor selected from the group of field-effect transistors or single electron transistors. The transistor includes a substrate, a source electrode disposed on the substrate and a drain electrode disposed on the substrate, and a channel forming a current path between the source electrode and the drawing electrode; an interaction-sensing gate comprising a specific substance; and a voltage gate. The method includes (a) providing the detection target on the interaction-sensing gate; (b) setting the gate voltage in the voltage gate at a predetermined level; (c) selectively interacting the specific substance with the detection target; (d) when the detection target interacts with the specific substance, changing a gate voltage in the voltage gate to adjust a characteristic of the transistor; and (e) measuring a change in the characteristic of the transistor to determine a presence of the detection target.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Japan Science and Technology Agency
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8772879
    Abstract: An electronic component including a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor includes a gate that has two electrodes, namely a first electrode embedded inside the substrate where the channel of the transistor is defined and a second upper electrode located above the substrate facing buried electrode relative to channel and separated from said channel by a layer of dielectric material and wherein the embedded electrodes of all the transistors are formed by an identical material, the upper electrodes having a layer that is in contact with the dielectric material which is formed by materials that differ from one subset of transistors to another.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 8, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Luc Huguenin, Stéphane Monfray
  • Patent number: 8759924
    Abstract: Various aspects of the technology provide a dual semiconductor power and/or switching FET device to replace two or more discrete FET devices. Portions of the current may be distributed in parallel to sections of the source and drain fingers to maintain a low current density and reduce the size while increasing the overall current handling capabilities of the dual FET. Application of the gate signal to both ends of gate fingers, for example, using a serpentine arrangement of the gate fingers and gate pads, simplifies layout of the dual FET device. A single integral ohmic metal finger including both source functions and drain functions reduces conductors and contacts for connecting the two devices at a source-drain node. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 24, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8753941
    Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Vijay K. Reddy, Samuel Martin, T Krishnaswamy
  • Patent number: 8753940
    Abstract: One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 17, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Dae Geun Yang
  • Patent number: 8735248
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-wook Lee, Myeong-cheol Kim, Heung-sik Park, Sang-min Lee, Hyun-ho Jung
  • Publication number: 20140127870
    Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the semiconductor core at the two terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
  • Patent number: 8709884
    Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthew T. Currie
  • Patent number: 8697502
    Abstract: A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6F2 saddle fin gate structure transistor, so that the size of a channel region increases. In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: defining an active region by forming a device isolation film over a semiconductor substrate; forming a first recess extending to a first level in the active region; forming a sacrificial film at a lower portion of the first recess; forming a fin structure over the sacrificial film; separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; and forming a gate to enclose the fin structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Young Man Cho
  • Publication number: 20140091403
    Abstract: A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 3, 2014
    Applicant: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 8673719
    Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Jeffrey W. Sleight
  • Patent number: 8669145
    Abstract: A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: March 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Diane C. Boyd, Huilong Zhu
  • Patent number: 8652910
    Abstract: In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Kyeong Kang, Jae-Seok Kim, Ho-Young Kim, Bo-Un Yoon, Il-Young Yoon
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus