Abstract: Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a higher deuterium concentration at an interface with the gate layer than at surface of the gate cap layer distal from the gate layer. In certain embodiments, the channel comprises polysilicon or recrystallized polysilicon. Other embodiments are also described.

Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Abstract: Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.

Abstract: Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.

Abstract: Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.

Abstract: A gate dielectric as formed includes a first interfacial dielectric layer and a high dielectric constant (high-k) dielectric layer containing a dielectric metal oxide. A polycrystalline semiconductor material layer is deposited on the high-k dielectric layer, and a second interfacial dielectric layer is formed at an interface between the polycrystalline semiconductor material layer and the high-k dielectric layer. A scavenging-metal-containing layer including a scavenging metal in an elemental form or in a metallic non-metal-element-containing compound is formed over the polycrystalline semiconductor material layer. A metallic compound such as a metallic nitride and a metallic carbide may be present above and/or over the scavenging-metal-containing layer. After formation of a gate stack by patterning, an anneal is performed, during which the oxygen in the interfacial dielectric layers diffuses into the scavenging-metal containing layer so that the thicknesses of the interfacial layers are reduced.

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a substrate, the first sacrificial patterns spaced apart from each other, forming a capping layer on the first sacrificial patterns, forming a gap insulating layer spaced apart from a lower portion of the capping layer between the first sacrificial patterns in a vertical direction, planarizing the gap insulating layer and the capping layer to expose the first sacrificial patterns, removing the first sacrificial patterns to form trenches, and forming conductive patterns in the trenches, the conductive patterns having an air gap therebetween and between the lower portion of the capping layer and the gap insulating layer.

Abstract: A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, a first charge trap layer on the interface insulating layer, and a second charge trap layer on the first charge trap layer, and a trap level of the second charge trap layer is lower than a trap level of the first charge trap layer.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor.

Abstract: A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract: Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced.

Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract: A gate dielectric as formed includes a first interfacial dielectric layer and a high dielectric constant (high-k) dielectric layer containing a dielectric metal oxide. A polycrystalline semiconductor material layer is deposited on the high-k dielectric layer, and a second interfacial dielectric layer is formed at an interface between the polycrystalline semiconductor material layer and the high-k dielectric layer. A scavenging-metal-containing layer including a scavenging metal in an elemental form or in a metallic non-metal-element-containing compound is formed over the polycrystalline semiconductor material layer. A metallic compound such as a metallic nitride and a metallic carbide may be present above and/or over the scavenging-metal-containing layer. After formation of a gate stack by patterning, an anneal is performed, during which the oxygen in the interfacial dielectric layers diffuses into the scavenging-metal containing layer so that the thicknesses of the interfacial layers are reduced.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance.

Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.

Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

Abstract: Nonvolatile memory has a modified channel region interface, such as a raised source and drain or a recessed channel region.

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

Abstract: A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract: Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells.

Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.

Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract: A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract: A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film.

Abstract: The present invention provides a method for forming a semiconductor structure having a metal connect. A substrate is provided, and a transistor and a first ILD layer are formed thereon. A first contact plug is formed in the first ILD layer to electrically connect the source/drain region. A second ILD layer and a third ILD layer are formed on the first ILD layer. A first opening above the gate and a second opening above the first contact plug are formed, wherein a depth of the first contact plug is deeper than that of the second opening. Next, the first opening and the second opening are deepened. Lastly, a metal layer is filled into the first opening and the second opening to respectively form a first metal connect and a second metal connect.

Abstract: After forming replacement gate structures that are embedded in a planarized dielectric layer on a semiconductor substrate, a contact-level dielectric layer is deposited over a planar surface of the planarized dielectric layer and the replacement gate structures. Substrate contact via holes are formed through the contact-level dielectric layer and the planarized dielectric layer, and metal semiconductor alloy portions are formed on exposed semiconductor materials. Gate contact via holes are subsequently formed through the contact-level dielectric layer. The substrate contact via holes and the gate contact via holes are simultaneously filled with a conductive material to form substrate contact structures and gate contact structures. The substrate contact structures and gate contact structures can be employed to provide local interconnect structures that provide electrical connections between two components that are laterally spaced on the semiconductor substrate.

Abstract: A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.

Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.

Abstract: According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter.

Abstract: The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

Abstract: A method for manufacturing a nitride-based semiconductor device includes: preparing a substrate; forming a buffer layer on the substrate, the buffer layer preventing dislocation with the substrate; forming a spacer on the buffer layer; forming a barrier layer on the spacer, the barrier layer forming a hetero-structure with the spacer; forming a protecting layer on the barrier layer; and forming an HfO2 layer the protecting layer through RF sputtering.

Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor regions each having a protruded shape provided on a substrate, the first semiconductor region including a first source, a first drain, and a first channel provided between the first source and the first drain and extending in a first direction from the first source to the first drain, the first channel having a first width in a second direction perpendicular to the first direction, and the second semiconductor region including a second source, a second drain, and a second channel provided between the second source and the second drain and extending in a third direction from the second source to the second drain, the second channel having a second width in a fourth direction perpendicular to the third direction that is wider than the first width of the first channel.

Abstract: According to one embodiment, a semiconductor device includes an active area that is formed on a semiconductor substrate, a trench that isolates the active area, a nitride film that is buried in the trench, an air gap that is formed above the nitride film along the trench, and a gate electrode that is formed on the active area to span the trench through the air gap.

Abstract: The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.

Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.

Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.

Abstract: A method comprises: forming a first array of fins and a second array of fins on a substrate; masking off the first array of fins from the second array of fins with a first mask; depositing a dielectric layer on the second array of fins and on the first mask on the first array of fins; masking off the dielectric layer deposited on the second array of fins with a second mask; removing the dielectric layer and the first mask from the first array of fins; removing the second mask from the second array of fins to expose the dielectric layer on the second array of fins; and depositing a chemox layer on the first array of fins. The chemox layer is thinner than the dielectric layer on the second array of fins.