Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound Patents (Class 438/287)
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Publication number: 20140127873Abstract: A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.Type: ApplicationFiled: November 7, 2013Publication date: May 8, 2014Applicant: STMICROELECTRONICS (ROUSSET) SASInventor: Philippe BOIVIN
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Patent number: 8716088Abstract: A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.Type: GrantFiled: June 27, 2012Date of Patent: May 6, 2014Assignees: International Business Machines Corporation, GLOBAL FOUNDRIES Inc.Inventors: Takashi Ando, Unoh Kwon, Vijay Narayanan, James K. Schaeffer
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Patent number: 8716089Abstract: A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.Type: GrantFiled: March 8, 2013Date of Patent: May 6, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
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Patent number: 8709902Abstract: In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any additional process steps by using a sacrificial spacer element as an etch mask and as an implantation mask for incorporating the drain and source dopant species for deep drain and source areas for one type of transistor. On the other hand, the usual main spacer may be used for the incorporation of the deep drain and source regions of the other type of transistor.Type: GrantFiled: July 28, 2011Date of Patent: April 29, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Thilo Scheiper, Kerstin Ruttloff, Maciej Wiatr, Stefan Flachowsky
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Patent number: 8703567Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.Type: GrantFiled: November 29, 2011Date of Patent: April 22, 2014Assignee: The Institute of Microelectronics Chinese Academy of ScienceInventors: Guilei Wang, Chunlong Li, Chao Zhao
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Patent number: 8704205Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.Type: GrantFiled: August 24, 2012Date of Patent: April 22, 2014Assignee: Macronix International Co., Ltd.Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih
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Publication number: 20140106530Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.Type: ApplicationFiled: December 21, 2013Publication date: April 17, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: KOTA FUNAYAMA, HIRAKU CHAKIHARA, YASUSHI ISHII
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Patent number: 8698228Abstract: According to one embodiment, a non-volatile memory device includes a stacked structure and a voltage application portion. The stacked structure includes a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion. The voltage application portion applies a voltage to the memory portion to cause a change in a resistance in the memory portion to store information. The surface includes a first region and a second region. The first region contains at least one of a metallic element, Si, Ga, and As. The first region is conductive. The second region contains at least one of the metallic element, Si, Ga, and As, and has a content ratio of nonmetallic element higher than a content ratio of nonmetallic element in the first region. At least one of the first region and the second region has an anisotropic shape on the surface.Type: GrantFiled: September 20, 2010Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Araki, Takeshi Yamaguchi, Mariko Hayashi, Kohichi Kubo, Takayuki Tsukamoto
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Patent number: 8692229Abstract: In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.Type: GrantFiled: July 26, 2012Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Guy M. Cohen, Michael A. Guillorn
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Patent number: 8692311Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution.Type: GrantFiled: September 20, 2011Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shinohara, Daigo Ichinose
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Patent number: 8691643Abstract: Methods of forming semiconductor devices are provided. The methods may include forming a gate pattern on an active region of a substrate. The methods may further include performing a deoxidization treatment on the substrate.Type: GrantFiled: September 22, 2011Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Kieun Kim, Yongkuk Jeong, Hyun-Kwan Yu
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Patent number: 8692312Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.Type: GrantFiled: March 23, 2012Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Masaru Kito, Takeshi Imamura
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Patent number: 8691645Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: GrantFiled: August 10, 2012Date of Patent: April 8, 2014Assignee: Spansion LLCInventors: Yukio Hayakawa, Hiroyuki Nansei
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Patent number: 8686490Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.Type: GrantFiled: February 20, 2009Date of Patent: April 1, 2014Assignee: SanDisk CorporationInventor: Jian Chen
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Patent number: 8679920Abstract: Semiconductor devices and methods of fabricating semiconductor devices that may include forming an insulation structure including insulation patterns that are sequentially stacked and vertically separated from each other to provide gap regions between the insulation patterns, forming a first conductive layer filling the gap regions and covering two opposite sidewalls of the insulation structure, and forming a second conductive layer covering the first conductive layer. A thickness of the second conductive layer covering an upper sidewall of the insulation structure is greater than a thickness of the second conductive layer covering a lower sidewall of the insulation structure.Type: GrantFiled: October 14, 2011Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hauk Han, Byoung-Kyu Lee, Jingi Hong, Changwon Lee, Eungjoon Lee, Je-Hyeon Park, Jeonggil Lee
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Publication number: 20140078832Abstract: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: EON SILICON SOLUTION, INC.Inventors: TAKAO AKAOGI, YIDER WU, YI-HSIU CHEN, HUNG-HUI LAI
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Patent number: 8673721Abstract: A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern.Type: GrantFiled: May 27, 2011Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Nakanishi Toshiro, Choong Man Lee
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Patent number: 8674457Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.Type: GrantFiled: August 11, 2010Date of Patent: March 18, 2014Assignee: Globalfoundries Singapore PTE., Ltd.Inventors: Eng Huat Toh, Elgin Quek, Chunshan Yin, Chung Foong Tan, Jae Gon Lee
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Publication number: 20140070303Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. Each of memory cell arrays includes a plurality of memory cells on the semiconductor substrate. Select gate transistors are provided on ends of the memory cell arrays and brought into conduction when the memory cells are connected to a corresponding line. An embedded impurity layer is embedded in active areas between the select gate transistors respectively corresponding to the memory cell arrays adjacent to each other. Contact plugs connect the embedded impurity layer and the lines.Type: ApplicationFiled: September 4, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenichi FUJII, Tooru Hara
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Publication number: 20140070330Abstract: In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.Type: ApplicationFiled: November 20, 2013Publication date: March 13, 2014Applicant: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Publication number: 20140070304Abstract: According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film.Type: ApplicationFiled: March 5, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Ken KOMIYA, Tatsuya KATO, Kenta YAMADA, Hidenobu NAGASHIMA
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Publication number: 20140070301Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A plurality of memory cells are provided on the semiconductor substrate. Peripheral circuits are provided on a periphery of the memory cells. A first barrier film includes a first nitride film provided on a first gate electrode of a transistor included in the peripheral circuits. A second barrier film includes a second nitride film different from the first nitride film. The second nitride film is provided on a second gate electrode of the memory cells, respectively. Metal layers are provided on the first and second barrier films, respectively.Type: ApplicationFiled: July 29, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahisa SONODA, Koichi Matsuno
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Publication number: 20140073103Abstract: A method of fabricating a semiconductor device includes providing a dummy gate insulation film formed on a substrate, the dummy gate insulation film including a first material and providing a spacer formed at least one side of the gate insulation film, the spacer including the first material, removing the first material included in the dummy gate insulation film by a first process, removing the dummy gate insulation film from which the first material has been removed by a second process different from the first process, and sequentially forming a gate insulation film and a gate electrode structure on the substrate.Type: ApplicationFiled: August 27, 2013Publication date: March 13, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Seok-Jun WON, Hyung-Suk JUNG
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Publication number: 20140061749Abstract: Disclosed are transparent non-volatile memory devices and methods of manufacturing the same. The method may include forming an active layer on a substrate, forming a source and a drain spaced apart from each other on the active layer, forming a gate insulating layer having quantum dots on the source, the drain, and the active layer, and forming a gate on the gate insulating layer between the source and the drain. The quantum dots and the gate insulating layer may be formed simultaneously.Type: ApplicationFiled: December 18, 2012Publication date: March 6, 2014Applicant: Electronics and Telecommunications Research InstituteInventor: Rae-Man PARK
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Publication number: 20140065776Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.Type: ApplicationFiled: August 12, 2013Publication date: March 6, 2014Applicant: Renesas Electronics CorporationInventor: Tatsuyoshi MIHARA
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Publication number: 20140061772Abstract: Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.Type: ApplicationFiled: November 11, 2013Publication date: March 6, 2014Inventors: Won-Cheol Jeong, Su-Jin Ahn, Yoon-Moon Park
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Publication number: 20140061768Abstract: According to one embodiment, a method for manufacturing is a method for manufacturing a nonvolatile semiconductor memory device including a memory string having series-connected memory cells. The method includes forming a first semiconductor layer; forming a first sacrificial layer and the bottom surface and the side surface being surrounded with the first semiconductor layer; forming a first insulating layer on the first semiconductor layer and the first sacrificial layer; forming a stacked body on the first insulating layer, the body including electrode layers and second sacrificial layers alternately stacked; forming a first trench extending from an upper surface of the body to the first insulating layer on the first sacrificial layer; forming a second insulating layer in the first trench; forming a second trench extending from the upper surface of the body to the first semiconductor layer; and forming a third insulating layer in the second trench.Type: ApplicationFiled: June 26, 2013Publication date: March 6, 2014Inventor: Hiroshi SHINOHARA
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Patent number: 8659071Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.Type: GrantFiled: December 20, 2012Date of Patent: February 25, 2014Assignee: Shanghai Huali Microelectronics CorporationInventor: Zhi Tian
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Patent number: 8659090Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.Type: GrantFiled: December 22, 2011Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-En Huang, Wun-Jie Lin, Ling-Chang Hu, Hsiao-Lan Yang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Fu-An Wu, Jung-Ping Yang, Cheng Hung Lee
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Patent number: 8658490Abstract: Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles.Type: GrantFiled: April 4, 2012Date of Patent: February 25, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Elke Erben, Martin Trentzsch, Richard J. Carter
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Patent number: 8658503Abstract: A semiconductor device includes: a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer provided on the first main surface of the silicon carbide substrate; first silicon carbide regions formed on a surface of the first silicon carbide layer; second and third silicon carbide regions formed on respective surfaces of the first silicon carbide regions; a fourth silicon carbide region formed between facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode; a first electrode electrically connected to the second and third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate.Type: GrantFiled: December 5, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kono, Takashi Shinohe
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Patent number: 8658501Abstract: In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.Type: GrantFiled: August 4, 2009Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Supratik Guha, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20140048891Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.Type: ApplicationFiled: January 10, 2013Publication date: February 20, 2014Applicant: Semiconductor Manufacturing International Corp.Inventor: Yong Chen
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Publication number: 20140048867Abstract: A device is disclosed. The device includes a substrate and a fin structure disposed on the substrate. The fin structure serves as a common body of n transistors. The transistors include separate charge storage layers and gate dielectric layers. The charge storage layers are disposed over a top surface of the fin structure and the gate dielectric layers are disposed on sidewalls of the fin structure. n=2x, x is a whole number greater or equal to 1. A transistor can interchange between a select transistor and a storage transistor.Type: ApplicationFiled: August 20, 2012Publication date: February 20, 2014Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Eng Huat TOH, Shyue Seng TAN, Khee Yong LIM, Elgin QUEK
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Publication number: 20140048865Abstract: A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.Type: ApplicationFiled: August 16, 2012Publication date: February 20, 2014Applicant: GLOBAL FOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat TOH, Khee Yong LIM, Shyue Seng TAN, Elgin QUEK
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Patent number: 8652890Abstract: Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.Type: GrantFiled: February 29, 2012Date of Patent: February 18, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Sven Schmidbauer, Dina H. Triyoso, Elke Erben, Hao Zhang, Robert Binder
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Publication number: 20140042559Abstract: A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.Type: ApplicationFiled: January 8, 2013Publication date: February 13, 2014Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.Inventors: YONG CHEN, YONGGEN HE
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Publication number: 20140036585Abstract: The present invention relates to a nonvolatile memory device and to a method for manufacturing same. According to the present invention, the blocking insulation layer of a nonvolatile memory device having a typical SONOS structure is replaced with a threshold voltage switching material, which changes to a low resistance state only while a voltage greater than a threshold voltage is applied while maintaining a high resistance state under normal conditions and returning to the high resistance state when the applied voltage is removed. The present invention performs a program operation by injecting charges from a gate electrode layer into a charge trap layer through an insulation layer formed of the threshold voltage switching material after applying a voltage pulse greater than the threshold voltage to the gate electrode layer.Type: ApplicationFiled: August 17, 2011Publication date: February 6, 2014Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATIONInventors: Taegeun Kim, Homyoung AN
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Patent number: 8637921Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.Type: GrantFiled: December 27, 2007Date of Patent: January 28, 2014Assignee: Cypress Semiconductor CorporationInventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick B. Jenne
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Publication number: 20140024190Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.Type: ApplicationFiled: September 20, 2013Publication date: January 23, 2014Applicant: Spansion LLCInventors: Fred CHEUNG, Hiroyuki Kinoshita, Chungho Lee, Yu Sun, Chi Chang
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Publication number: 20140024189Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.Type: ApplicationFiled: July 17, 2013Publication date: January 23, 2014Inventors: Bi-O Kim, Toshiro Nakanishi, Jin-Tae Noh, Chang-Woo Sun, Seung-Hyun Lim, Jae-Young Ahn, Ki-Hyun Hwang
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Patent number: 8633079Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.Type: GrantFiled: January 20, 2010Date of Patent: January 21, 2014Assignee: United Microelectronics Corp.Inventors: Ping-Chia Shih, Yu-Cheng Yin
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Patent number: 8633118Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.Type: GrantFiled: February 1, 2012Date of Patent: January 21, 2014Assignee: Tokyo Electron LimitedInventor: Robert D Clark
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Patent number: 8633534Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.Type: GrantFiled: December 22, 2010Date of Patent: January 21, 2014Assignee: Intel CorporationInventors: Michael G. Haverty, Sadasivan Shankar
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Patent number: 8633098Abstract: The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.Type: GrantFiled: September 28, 2010Date of Patent: January 21, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Kai Han, Wenwu Wang, Xiaolei Wang, Shijie Chen, Dapeng Chen
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Publication number: 20140017867Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.Type: ApplicationFiled: September 11, 2013Publication date: January 16, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ssu-I Fu, I-Ming Tseng, En-Chiuan Liou, Cheng-Guo Chen
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Patent number: 8629025Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.Type: GrantFiled: February 23, 2012Date of Patent: January 14, 2014Assignee: United Microelectronics Corp.Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
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Patent number: 8629028Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.Type: GrantFiled: February 22, 2013Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Christopher V. Baiocco, Daniel J. Jaeger, Carl J. Radens, Helen Wang
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Patent number: 8629022Abstract: A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.Type: GrantFiled: March 15, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Sunfei Fang, Yue Liang, Xiaojun Yu, Jun Yuan
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Patent number: 8629007Abstract: A method of making a gate of a field effect transistor (FET) with improved fill by a replacement gate process using a sacrificial film includes providing a substrate with a dummy gate. It further includes depositing a sacrificial layer and an encapsulating layer over the substrate, and planarizing so that the encapsulating layer, sacrificial layer and dummy gate are co-planar. The encapsulating layer and a portion of the sacrificial film are removed to leave a remaining sacrificial film. The dummy gate is removed to form and opening in the remaining sacrificial film and to expose sidewalls of the film. Spacers are formed on the sidewalls. A high dielectric constant film and metal film are deposited in the opening and planarized to form a gate. The remaining sacrificial film is removed. The method can be used on planar FETs as well non-planar FETs.Type: GrantFiled: July 14, 2011Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Balasubramanian S. Haran, James J. Demarest