Dielectric Isolation Formed By Grooving And Refilling With Dielectric Material Patents (Class 438/296)
  • Patent number: 10766617
    Abstract: Methods and apparatus to grasp an object with an unmanned aerial vehicle are described herein. An example unmanned aerial vehicle includes a gripper having a claw to grasp onto an object and an active material disposed on the claw. The example unmanned aerial vehicle further includes a material activator to: (1) apply an activation signal to the active material to soften the active material while the claw grasps the object with the active material, and (2) allow the active material to harden in a shape substantially matching a surface of the object.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventor: Paul Gwin
  • Patent number: 10707134
    Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 7, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ji Quan Liu
  • Patent number: 10643999
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Patent number: 10634629
    Abstract: A method and system to develop the age and history of a crack by exposing a specimen or component to varying predetermined temperature range that covers the designated service temperatures and measuring the thickness of the oxide across the specimen along the thickness direction.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 28, 2020
    Assignees: Board of Trustees of the University of Arkansas, Chun-Ang University Industry-Academic Cooperation Foundation
    Inventors: Ashok Saxena, Ralph Edward Huneycutt, IV, Kee Bong Yoon
  • Patent number: 10615164
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Patent number: 10559595
    Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yamamoto
  • Patent number: 10505053
    Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 10483321
    Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Yih Wang, Patrick Morrow
  • Patent number: 10475839
    Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Yun-Wei Cheng, Kuo-Cheng Lee, Chun-Hao Chou, Yung-Lung Hsu
  • Patent number: 10431681
    Abstract: A semiconductor device includes a gate trench of at least one transistor structure extending into a semiconductor substrate. The gate trench includes at least one sidewall having a bevel portion located adjacent to a bottom of the gate trench. The at least one sidewall of the gate trench is formed by the semiconductor substrate. An angle between the bevel portion and a lateral surface of the semiconductor substrate is between 110? and 160°. A lateral dimension of the bevel portion is larger than 50 nm. Methods for forming the semiconductor device are also provided.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Patent number: 10347547
    Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 9, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Seshasayee Varadarajan, Aaron R. Fellis, Andrew John McKerrow, James Samuel Sims, Ramesh Chandrasekharan, Jon Henri
  • Patent number: 10290549
    Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Julien Frougier, Min Gyu Sung, Edward Joseph Nowak, Nigel G. Cave, Lars Liebmann, Daniel Chanemougame, Andreas Knorr
  • Patent number: 10141373
    Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Song-Yi Kim, Jae-Kyu Lee, Dae-Hwan Kang, Gwan-Hyeob Koh
  • Patent number: 10134903
    Abstract: A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed adjacent respective sidewalls of the semiconductor substrate. The method forms dielectric material separating the gate electrodes from the source and drain regions.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 20, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Xiuyu Cai, Chun-chen Yeh, Ruilong Xie
  • Patent number: 10096672
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Meng-Yi Wu, Yung-Fa Lee, Ying-Lang Wang
  • Patent number: 10056293
    Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10008412
    Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 26, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Annamalai Lakshmanan, Ben-Li Sheu, Guodan Wei, Nicole Lundy, Paul F. Ma
  • Patent number: 9953874
    Abstract: An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9941279
    Abstract: A semiconductor structure includes a substrate, at least one active fin present on the substrate, and at least one isolation dielectric surrounding the active fin. The isolation dielectric has at least one trench therein. The semiconductor structure further includes at least one dielectric liner present on at least one sidewall of the trench of the isolation dielectric, and at least one filling dielectric present in the trench of the isolation dielectric.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Patent number: 9929023
    Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Do, Jonghoon Jung, Sanghoon Baek, Seungyoung Lee, Taejoong Song, Jinyoung Lim
  • Patent number: 9917150
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9837404
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie, Kwan-Yong Lim
  • Patent number: 9735232
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-I Yang, Jheng-Sheng You, Chi-Fu Lin, Tien-Lu Lin
  • Patent number: 9679984
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer. The metal layer includes aluminum.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chin Chung, Shiang-Rung Tsai, Hsien-Ming Lee, Cheng-Lung Hung, Hsiao-Kuan Wei
  • Patent number: 9679816
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9647118
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a trench in the substrate, where a bottom surface of the trench has a first crystal plane orientation and a side surface of the trench has a second crystal plane orientation, and epitaxially (epi) growing a semiconductor material in the trench. The epi process utilizes an etch component. A first growth rate on the first crystal plane orientation is different from a second growth rate on the second crystal plane orientation.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manaufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 9634125
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Patent number: 9620642
    Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Kiok Boone Quek
  • Patent number: 9570548
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9508596
    Abstract: During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 29, 2016
    Assignee: Vishay-Siliconix
    Inventors: Naveen Tipirneni, Deva Pattanayak
  • Patent number: 9502280
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Patent number: 9472655
    Abstract: An improvement is made in the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film covering a control gate electrode, and a dummy memory electrode gates are formed, and then a diffusion region on a source-region-side of a memory to produced is formed across the dummy memory electrode gates. Subsequently, the dummy memory electrode gates is removed, and then a memory gate electrode is formed which is smaller in gate length than the dummy memory electrode gates. Thereafter, an extension region on the source-region-side of the memory is formed.
    Type: Grant
    Filed: February 6, 2016
    Date of Patent: October 18, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 9472554
    Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Michael Hargrove, Yanxiang Liu, Christian Gruensfelder
  • Patent number: 9431413
    Abstract: The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao
  • Patent number: 9419039
    Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 16, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Nayera Ahmed, Francois Roy
  • Patent number: 9419096
    Abstract: A method of manufacturing a transistor by which sufficient stress can be applied to a channel region within allowable ranges of concentrations of Ge and C in a mixed crystal layer.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: August 16, 2016
    Assignee: SONY CORPORATION
    Inventor: Yasushi Tateshita
  • Patent number: 9373681
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Patent number: 9324618
    Abstract: One illustrative method includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a substrate fin, forming a layer of insulating material in the trenches, and forming a layer of CTE-matching material above the upper surface of the layer of insulating material, wherein the layer of CTE-matching material has a CTE that is within ±20% of the replacement fin CTE and wherein the layer of CTE-matching material partially defines a replacement fin cavity that exposes an upper portion of the substrate fin. In this example, the method also includes forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: April 26, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Bruce Doris
  • Patent number: 9293507
    Abstract: An electronic device includes a semiconductor device that includes: a substrate including a switching element having a buried gate electrode; a buried decoupling capacitor having a line width same as a line width of the buried gate electrode; and a variable resistance element, electrically coupled to the switching element, formed over the substrate.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SK hynix Inc.
    Inventors: Joon-Seop Sim, Seok-Pyo Song, Jae-Yun Yi
  • Patent number: 9245943
    Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: January 26, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz Josef Niedernostheide, Reinhart Job
  • Patent number: 9236258
    Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Andy C. Wei, Qi Zhang, Ajey Poovannummoottil Jacob, Michael Hargrove
  • Patent number: 9166016
    Abstract: Provided is a method for fabricating a semiconductor device including the following steps. A silicon-containing conductive layer is formed on a substrate. Then, a dielectric layer is formed around the silicon-containing conductive layer. A portion of the dielectric layer is removed to expose a first sidewall of the silicon-containing conductive layer. A shielding structure is formed on a partial surface of the silicon-containing conductive layer, and the shielding structure exposes at least the first sidewall. A metal layer is formed on the substrate to cover the silicon-containing conductive layer not covered by the shielding structure. A salicide process is performed to form a silicide layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 20, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chi-Sheng Peng, Chia-Wen Cheng
  • Patent number: 9136327
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Patent number: 9117876
    Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: August 25, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Grégory Bidal, Laurent Favennec, Raul Andres Bianchi
  • Patent number: 9111994
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 18, 2015
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventors: Yong-sik Won, Sang-uk Lee
  • Patent number: 9099380
    Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: August 4, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vara Govindeswara Reddy Vakada, Laegu Kang, Michael P. Ganz, Yi Qi, Puneet Khanna, Sri Charan Vemula, Srikanth Samavedam
  • Patent number: 9087915
    Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Sameer Pradhan, Jeanne Luce
  • Publication number: 20150145000
    Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Ran Yan, Nicolas Sassiat, Alban Zaka, Kun-Hsien Lin
  • Patent number: 9040379
    Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Publication number: 20150137251
    Abstract: A semiconductor device includes a substrate and a device isolation pattern extending from a surface of the substrate into the substrate. The device isolation pattern has an electrically negative property and a physically tensile property. The device isolation pattern delimits an active region of the substrate. A transistor is provided at the active region and has a channel region formed by part of the active region.
    Type: Application
    Filed: August 7, 2014
    Publication date: May 21, 2015
    Inventors: SUNGHEE LEE, EUI-CHUL JEONG, NARA KIM, SEUNG HWAN KIM, DONGWOO WOO, SANGHOON LEE, SUNGJOO LEE