Abstract: A method of fabricating a dynamic random memory. On a semiconductor substrate comprising a memory cell region and a periphery circuit region, a first field implantation and a first anti-punch through implantation are performed. Using a photo-resist layer formed to cover the memory cell region as a mask, the periphery circuit region is performed with a second field implantation and a second anti-punch through implantation.

Abstract: A semiconductor device includes a first conductivity type low concentration impurity layer provided around a thick silicon oxide film, which is formed for element isolation in a first conductivity type element region as a surface region in a semiconductor substrate, and a second conductivity type impurity layer which is provided immediately under at least the thick silicon oxide film. The second conductivity type impurity layer constitutes a channel stopper to enhance the effect of element isolation. The first conductivity type low concentration impurity layer has an effect of improving the P-N junction breakdown voltage of an active region in the first conductivity type element region, and suppresses the narrow channel effect of a MOS transistor in the first conductivity type element region.

Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract: Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.

Abstract: After a field oxide film is formed on a P-type semiconductor substrate, ion implantation of boron is carried out with respect to a whole surface of the substrate so that a channel stopper layer is formed. Then, a MOS FET is formed in an active region of the semiconductor substrate. Subsequently, ion implantation of phosphorus is carried out, by using a gate electrode of the MOS FET and the field oxide film as a mask, so that impurity layers which have the same type of conductivity as that of the channel stopper layer and has a concentration lower than that of the channel stopper layer are formed right under the source/drain regions of the MOS FET between the source/drain regions and the channel stopper layer.

Abstract: A method of fabricating a semiconductor device having a trench isolation structure includes forming an isolation region including a trench and a trench plug for filling the trench so as to define active regions on a substrate, a part of the trench plug projecting upward from the surface of the substrate, forming sidewall spacers from an oxidative material on the sidewalls of the projecting portion of the trench plug, and oxidating the surface of the active region of the substrate and the sidewall spacers so as to form a gate insulating layer extending to the upper part of the active region of the substrate and the side surfaces of the trench plug.

Abstract: A semiconductor device includes a substrate having an active region between field oxide films, a gate formed on the substrate with a gate oxide therebetween, and a first impurity region formed adjacent to each side of the gate. A second impurity region is formed between the field oxide film and the first impurity region and a first insulating film with a contact hole exposes portions of the first and second impurity regions. An electrode formed in the contact hole such that the portions of the first and second impurity regions overlap an area in the substrate beneath the electrode.

Abstract: In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is formed over the gate electrode. Portions of the relatively thick oxide layer are removed to expose a region of the substrate adjacent the gate electrode. The exposed region is then doped with a dopant to form an active region. The active region may form an LDD region. The relatively thick oxide layer may comprise a contact formation layer.

Abstract: In a method of manufacturing a semiconductor device, a first oxide film is formed on a semiconductor substrate of the first conductivity type by using, as a mask, an oxidation preventing film formed in an element formation region. The oxidation preventing film is selectively etched and removed by using a patterned resist as a mask, thereby exposing the surface of the semiconductor substrate. An impurity of the second conductivity type is implanted in an exposed portion of the semiconductor device by using the resist as a mask, thereby forming an impurity diffusion layer of the second conductivity type. Thermal oxidation is performed while leaving the oxidation preventing film after the resist is removed, thereby forming a second oxidation film having a predetermined thickness on the surface of the impurity diffusion layer. Thermal oxidation is performed after the oxidation preventing film is removed, thereby forming a third thin oxide film on the surface of the semiconductor substrate.

Abstract: A method forms, in a CMOS semiconductor substrate, P- and N-wells having independently optimized field regions and active regions. In one embodiment, P- and N-wells are formed by (i) creating in successive steps the field regions of the P- and N-wells; (ii) creating an oxide layer over the field regions, (iii) creating in successive steps the active regions. The method achieves the P- and N-wells without increasing the number of photoresist masking steps. In addition, optical alignment targets (OATs) are optionally formed simultaneously with these P- and N-wells without increasing the total number of process steps.

Abstract: A semiconductor device includes a field insulating film, a channel stopper, and a diffusion layer. The field insulating film is formed on one major surface of a semiconductor substrate of a first conductivity type to surround an element region. The channel stopper of the first conductivity type is formed immediately below the field insulating film. The diffusion layer of an opposite conductivity type is formed to be adjacent to the channel stopper. The impurity concentration peak position of the diffusion layer substantially coincides with that of the channel stopper.

Abstract: An isolation layer forming method for a semiconductor device which prevents damage of an isolation layer due to a misalignment of a mask when a contact hole is formed. An anti-oxidative pattern for exposing an isolation region is formed on a semiconductor substrate, and an undercut portion on a lower sidewall of the anti-oxidative pattern is formed by selectively removing the exposed semiconductor substrate by an isotropic etching process. Thereafter, the isolation layer is formed by an oxidation process so that an edge portion of the isolation layer which is placed in the undercut portion is not exposed to a surface of the semiconductor substrate.

Abstract: A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the substrate comprising a second bulk region having a blanket doping of a second conductivity type dopant; b) defining field oxide regions and active area regions in each of the first and second bulk substrate regions; c) in the same masking step, masking active area regions of the first bulk substrate region while leaving field oxide regions of the first bulk substrate region unmasked and masking field oxide regions of the second bulk substrate region while leaving select active area regions of the second bulk substrate region unmasked; and d) in the same ion implanting step, ion implanting first conductivity type impurity through the unmasked portions of the first and second bulk substrate regions to simultaneously form channel stop isolation implants beneath t

Abstract: Short channel MOS semiconductor devices are produced by implanting impurity ions through gate electrode and gate oxide layers, before patterning the gate electrode, using a composite mask of silicon oxide and silicon nitride, to form a shallow channel region in the substrate for adjusting the threshold voltage and a deeper well region for preventing punch through. In another embodiment, impurity ions are implanted to form lightly doped and heavily doped source/drain regions in a single ion implantation step using a thermally grown oxide region having bird's beaks as a mask. Self-aligned lightly doped regions are formed under the bird's beaks.

Abstract: A microcoil structure for use in an integrated circuit to produce magnetic flux for specific applications or to serve as an inductor is provided. Further, a method for forming the foregoing microcoil structure in a semiconductor wafer is provided. The microcoil structure includes a plurality of diffusion regions having two ends formed with ohmic contact regions. A field-oxide region and an overlaying insulating layer are formed over the diffusion regions. The field oxide region and the insulating layer together serve as a core member for the microcoil structure Further, a plurality of conductive layers are electrically connected between the diffusion regions in such a manner as to form a coil-like structure which winds around the core member to form the desired microcoil structure. When current is input to this microcoil structure, a magnetic flux is produced. The magnitude and polarity of the magnetic flux can be controlled by varying the magnitude and direction of the input current.

Abstract: An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller .DELTA.W characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. The process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.

Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.

Abstract: A method for isolating elements in semiconductor devices is disclosed, which includes the steps of: forming a field oxide layer on the surface of a semiconductor substrate; using a photo resist pattern to define a field region and an active region; carrying out an ion implantation of several MeV with the photo resist pattern remaining on the field region, so as to form a channel stop layer on the field oxide layer region; and forming a soft error-preventing buried layer in the active region. The field insulating layer may be a silicon oxide layer or a silicon nitride layer. Additionally, a selective epitaxial process may be carried out so as to raise the level of the active region to substantially the height of the field isolating region, thereby flattening the surface.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Abstract: Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions.

Abstract: Methods of forming semiconductor active regions having channel-stop regions therein include the steps of forming an oxide layer and first nitride layer on a face of a semiconductor substrate and then patterning the first nitride layer to expose first portions of the oxide layer. The patterned first nitride layer is then used as a mask during implantation of dopants of second conductivity type into the substrate. A second nitride layer is then deposited on the exposed first portions of the oxide layer and on the first nitride layer. A second photoresist layer is then patterned and used as a mask to etch the second nitride layer and patterned first nitride layer, to expose second portions of the oxide layer. A third photoresist layer is then patterned to cover the first portions of the oxide layer. The patterned third photoresist layer and remaining portions of the patterned first and second nitride layers are then used as implant masks during implantation of second conductivity type dopants.

Abstract: A PMOS device has an n-type body 12 and a triple source drain diffusion. A first drain region 14 is heavily p-doped to provide ohmic contact to the drain. A lightly doped drain region 16 extends to and beneath a portion of the gate 20. A third shallow moderately p-doped region 50 extends from beneath a portion of the gate into the second lightly doped region. The third region 50 counteracts a radiation induced gate inversion layer and reduces the on resistance of the PMOS device.

Abstract: There are disclosed methods for the fabrication of semiconductor device. A junction leakage or defect which is generated at the bird's beak of field oxide film when forming an oxide film spacer at the side wall of a gate electrode in a MOSFET can be prevented by implanting a low density dopant or by sequentially implanting a high density dopant and a low density dopant into the substrate, subsequent to formation of the oxide film spacer.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: A semiconductor device includes a semiconductor substrate having low impurities of a first conductivity type including a field region and an active region, a first conductivity type region of high impurities at the field region of the semiconductor substrate, a first insulation film on the first conductivity type region of high impurities, a gate electrode at the active region of the semiconductor substrate, a second conductivity type region of high impurities on a central region of the semiconductor substrate between the gate electrode and the first insulation film, and second conductivity type regions of low impurities between the gate electrode and the second conductive type region of high impurities, and between the first insulation film and the second conductivity type region of high impurities.

Abstract: A high-voltage MOS (metal-oxide semiconductor) device and a method for fabricating the same is provided. The high-voltage MOS device features the forming of trench-type source/drain regions by the use of silicon nitride layers to conduct a self-alignment etching process on a polysilicon conductive layer. In addition, an insulating layer is formed between the source/drain regions and the substrate, which prevents the breakdown at the junction between the source/drain regions and the substrate and also prevent the occurrence of leakage current therein. The forming of metal contact windows on the source/drain regions over isolation layers also allows the prevention of over etching, the occurrence of metal spikes, and misalignment of critical dimensions on the substrate. The thus fabricated high-voltage MOS device is therefore more reliable.

Abstract: The present invention relates to a semiconductor isolation method for high density semiconductor(devices of which the isolation pitch is below 0.5 .mu.m. The present invention provides the semiconductor isolation method to improve the isolating characteristics of the semiconductor device by separately performing the isolation process for the area where the isolation pitch is wide from the area where it is narrow.

Abstract: A semiconductor processing method of providing dopant impurity into a semiconductor substrate includes: a) providing a semiconductor substrate, the substrate comprising a first bulk region having a blanket doping of a first conductivity type dopant, the substrate comprising a second bulk region having a blanket doping of a second conductivity type dopant; b) defining field oxide regions and active area regions in each of the first and second bulk substrate regions; c) in the same masking step, masking active area regions of the first bulk substrate region while leaving field oxide regions of the first bulk substrate region unmasked and masking field oxide regions of the second bulk substrate region while leaving select active area regions of the second bulk substrate region unmasked; and d) in the same ion implanting step, ion implanting first conductivity type impurity through the unmasked portions of the first and second bulk substrate regions to simultaneously form channel stop isolation implants beneath t

Abstract: A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

Abstract: A method of manufacturing a semiconductor device is disclosed. After an insulating film having an opening is formed on a first thin tungsten film, an impurity is introduced into the substrate through the opening to form a punch-through stopper between a source and a drain. Then, on the first tungsten film inside the opening, a second tungsten film is selectively deposited to form a gate electrode. With this method, it is possible to easily fabricate high-speed MOSFETs whose channel length is less than half a micron.

Abstract: An element separating oxide film is formed in a surface of a p-type silicon substrate for separation of an element forming region. A p-type impurity diffusion region extends from the vicinity of a lower surface of the element separating oxide film to a position at a predetermined depth in the element forming region. The p-type impurity diffusion region has a peak of concentration of impurity. In the element forming region adjacent to the element separating oxide film, an n.sup.+ impurity diffusion region is formed on the surface of the p-type silicon substrate. An n.sup.- impurity diffusion region adjacent to the n.sup.+ impurity diffusion region is formed between the n.sup.+ impurity diffusion region and the p-type impurity diffusion region.

Abstract: A method and system for providing a semiconductor device with device isolation and leakage current control which entails processing a semiconductor substrate to form a semiconductor circuit, and providing at least one high energy implant on the semiconductor circuit is disclosed. The high energy implant is provided at an angle to source and drain regions of the semiconductor circuit so as to allow a dosage from the at least one high energy implant below and away from the surface of the active device region. In so doing, a profile is provided in which dopant distribution is substantially uniform. Therefore, the breakdown characteristics are increased and the junction capacitance of the device is reduced. Accordingly, a device manufactured in accordance with the present invention has significant advantages over devices manufactured in accordance with conventional processes.

Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.