Oblique Implantation Patents (Class 438/302)
  • Patent number: 10164087
    Abstract: To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Senichirou Nagase, Tsuyoshi Kachi, Yoshinori Hoshino
  • Patent number: 10062770
    Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Shih-Hung Tsai
  • Patent number: 9391091
    Abstract: An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B Doris, Pranita Kerber, Ali Khakifirooz
  • Patent number: 9368347
    Abstract: A method irradiates a wafer and an apparatus provides for a wafer to be irradiated. A plurality of radiation emitters emit radiation. A mask permits a portion of the electromagnetic radiation from the plurality of radiation emitters to pass and blocks a further portion of said electromagnetic radiation from passing.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 14, 2016
    Inventor: Thomas Christ Dimitriadis
  • Patent number: 9224850
    Abstract: In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Goto, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiyuki Kondo
  • Patent number: 9196706
    Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Tianchun Ye, Huajie Zhou, Gaobo Xu, Qingqing Liang
  • Patent number: 8999802
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; selectively etching end portions of the gate dielectric layer to form gaps; and filling a material for the gate dielectric layer into the gaps.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yunfei Liu, Haizhou Yin
  • Patent number: 8999801
    Abstract: A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Ota, Masumi Saitoh, Toshinori Numata
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8994107
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: El Mehdi Bazizi, Francis Benistant
  • Publication number: 20150056776
    Abstract: A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 26, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei TATEMICHI, Takeyoshi NISHIMURA
  • Publication number: 20150044847
    Abstract: A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°.
    Type: Application
    Filed: September 18, 2014
    Publication date: February 12, 2015
    Inventors: Zhiqiang WU, Yi-Ming SHEU, Tsung-Hsing YU, Kuan-Lun CHENG, Chih-Pin TSAO, Wen-Yuan CHEN, Chun-Fu CHENG, Chih-Ching WANG
  • Publication number: 20150014770
    Abstract: A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Inventors: Vijay PARTHASARATHY, Sujit BANERJEE
  • Patent number: 8927376
    Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Patent number: 8912612
    Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8906759
    Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Sanjay Mehta, Tenko Yamashita, Chun-Chen Yeh
  • Publication number: 20140357042
    Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Ralf Richter, Stefan Flachowsky, Jan Hoentschel
  • Patent number: 8900954
    Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 8883578
    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Chun-chen Yeh, Tenko Yamashita
  • Patent number: 8877596
    Abstract: a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Darshana N. Bhagat, Thomas J. Dunbar, Yen Li Lim, Jed H. Rankin, Eva A. Shah
  • Patent number: 8871585
    Abstract: A manufacturing method of a semiconductor device includes: forming a first gate insulating film on a semiconductor substrate in first and second regions in an active area; forming first gate electrodes on the first gate insulating film in the first and second regions; forming source/drain regions by introducing impurities at both sides of the first gate electrode in the first and second regions; performing heat treatment of activating the impurities; forming a stress liner film so as to cover the whole surface of first gate electrodes in the first and second regions; removing the stress liner film at an upper portion of the first gate electrode in the second region while allowing the stress liner film at least at a portion in the first region to remain to expose the upper portion of the first gate electrode in the second region; forming a groove by removing the first gate electrode in the second region; and forming a second gate electrode in the groove.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 28, 2014
    Assignee: Sony Corporation
    Inventor: Masanori Tsukamoto
  • Patent number: 8859380
    Abstract: A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Yi-Ming Sheu, Tsung-Hsing Yu, Kuan-Lun Cheng, Chih-Pin Tsao, Wen-Yuan Chen, Chun-Fu Cheng, Chih-Ching Wang
  • Patent number: 8841178
    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Chun-chen Yeh, Tenko Yamashita
  • Patent number: 8835290
    Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Dynaloy, LLC
    Inventors: Kimberly Dona Pollard, Allison C. Tonk
  • Patent number: 8835269
    Abstract: A method of manufacturing a solid-state image sensor having photoelectric conversion elements and one or more MOS transistors are formed on a semiconductor substrate is provided. The method includes forming a resist pattern having an opening and a shielding portion over the substrate; and implanting ions in the substrate through the opening. When the substrate is viewed from a direction, an isolation region that is positioned between accumulation regions adjacent to one another is exposed in the opening, and when viewed from a different direction, a channel region of the MOS transistors is exposed in the opening, and the isolation region is shielded by the shielding portion. Ions irradiated in the direction are implanted in the isolation region, and ions irradiated in the different direction are implanted in the channel region.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Junji Iwata
  • Patent number: 8828831
    Abstract: Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8822297
    Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tsung-Han Lee, Cheng-Tung Huang, Yi-Han Ye
  • Publication number: 20140206170
    Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Han Lee, Cheng-Tung Huang, Yi-Han Ye
  • Patent number: 8785287
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: July 22, 2014
    Assignee: Globalfoundries Singapore Pte, Ltd.
    Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan
  • Patent number: 8754448
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: June 17, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Patent number: 8741720
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Publication number: 20140117446
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
  • Publication number: 20140113425
    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, at least a gate structure is formed on a substrate. Subsequently, a first material layer and a second material layer sequentially formed on the substrate conformally cover the gate structure. Subsequently, an implantation process is performed on the second material layer, and a wet etching process is further performed to remove a part of the second material layer to form a remaining second material layer. Furthermore, a dry etching process is performed to remove a part of the remaining second material layer to form a partial spacer.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 8703552
    Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Publication number: 20140087538
    Abstract: A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; selectively etching end portions of the gate dielectric layer to form gaps; and filling a material for the gate dielectric layer into the gaps.
    Type: Application
    Filed: July 30, 2012
    Publication date: March 27, 2014
    Applicant: Institue of Microelectronics Chinese Academy of Sciences
    Inventors: Yunfei Liu, Haizhou Yin
  • Patent number: 8679884
    Abstract: A method for manufacturing a semiconductor apparatus includes the first step of forming a silicon oxide film including a main portion on a second portion and a sub portion between a first portion and a silicon nitride film, the second step of forming a first conductivity type impurity region under the silicon oxide film, and the third step of forming a semiconductor element including a second conductivity type impurity region having an opposite conductivity to the first conductivity type impurity region in the first portion. In the second step, angled ion implantation is performed into a region under the sub portion at an implantation angle using the silicon nitride film as a mask.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuhiro Kawabata
  • Patent number: 8669170
    Abstract: Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ricardo P. Mikalo, Stefan Flachowsky
  • Patent number: 8664072
    Abstract: In sophisticated P-channel transistors, which may frequently suffer from a pronounced surface topography of the active regions with respect to the surrounding isolation regions, superior performance may be achieved by using a tilted implantation upon forming the deep drain and source regions, preferably with the tilt angle of 20 degrees or less, thereby substantially avoiding undue lateral dopant penetration into sensitive channel areas.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Thilo Scheiper
  • Patent number: 8658506
    Abstract: Methods and apparatus for selectively improving integrated circuit performance are provided. In an example, a method is provided that includes defining a critical portion of an integrated circuit layout that determines the speed of an integrated circuit, identifying at least a part of the critical portion that includes at least one of a halo, lightly doped drain (LDD), and source drain extension (SDE) implant region, and performing a speed push flow process to increase performance of the part of the critical portion that includes the at least one of the halo, the LDD, and the SDE implant region. The resultant integrated circuit can be integrated with a mobile device.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Choh fei Yeap, Ping Liu
  • Patent number: 8652916
    Abstract: A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Roger A. Booth, Jr., Paul Chang, Kangguo Cheng, Chengwen Pei, William R. Tonti
  • Publication number: 20140035049
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device is formed on a substrate and includes a first first-type metal-oxide-semiconductor field effect transistor (MOSFET) and a second first-type MOSFET. The first first-type MOSFET includes a first gate structure, a first source area and a first drain area on the substrate. The second first-type MOSFET includes a second gate structure, a second source area, and a second drain area on the substrate. A first pocket implant process is applied to the first first-type MOSFET via a first photomask, while a second pocket implant process is applied to the second first-type MOSFET via a second photomask. The first and second gate structures are facing different directions.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 6, 2014
    Applicant: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ta-Hsun YEH, Hui-Min HUANG, Yuh-Sheng JEAN
  • Patent number: 8643107
    Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Chung-Hsun Lin, Josephine B. Chang, Leland Chang
  • Publication number: 20140017870
    Abstract: Disclosed herein is a method for inhibiting a programming disturbance of a flash memory, which relates to a technical field of a non-volatile memory in ultra-large-scale integrated circuit fabrication technologies. In the present invention, an dopant gradient of a PN junction between a substrate and a drain is reduced by adding a step of performing an angled ion implantation of donor dopants into a standard process for a flash memory, so that an electric field of the PN junction between the substrate and the drain is reduced, and consequently the programming disturbance is inhibited. Meanwhile, a dopant gradient of the PN junction between a channel and the drain is maintained, so that an electric field of the PN junction between the channel and the drain, which is necessary for programming, is maintained, and thus the programming efficiency and the programming speed can be ensured.
    Type: Application
    Filed: October 28, 2011
    Publication date: January 16, 2014
    Applicant: PEKING UNIVERSITY
    Inventors: Yimao Cai, Ru Huang
  • Patent number: 8614134
    Abstract: In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 24, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Gerhardt, Peter Javorka, Juergen Faul
  • Publication number: 20130323891
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Chung-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
  • Patent number: 8598007
    Abstract: One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: December 3, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8580646
    Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack A. Mandelman, William R. Tonti
  • Publication number: 20130295742
    Abstract: A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Jeffrey B. Johnson, Chung H. Lam, Beth A. Lawrence, Michael J. Zierak
  • Patent number: 8574989
    Abstract: The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Buh-Kuan Fang, Jr-Jung Lin, Ryan Chia-Jen Chen
  • Publication number: 20130244388
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Stefan Flachowsky, Shesh Mani Pandey