Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract: One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

Abstract: The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a gate stack on a semiconductor substrate. In the method, a first halo implantation is performed on the semiconductor substrate with a first dose of dopant ions to form first halo regions therein. A second halo spacer is formed around the gate stack. Then a second halo implantation is performed on the semiconductor substrate with a second dose of dopant ions to form second halo regions therein.

Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.

Abstract: A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Abstract: A semiconductor device manufacturing method includes: forming a first active region and a second active region in a semiconductor substrate; forming a first gate insulating film on the first active region and a second gate insulating film thinner than the first gate insulating film on the second active region by using material containing silicon oxide; forming first and second gate electrodes on the first and second gate insulating films respectively; forming an insulating film on the semiconductor substrate, and anisotropically etching the insulating film to leave first side wall insulating films on side walls of the first and second gate electrodes; removing the first side wall insulating film on the first gate electrode; and after removing the first side wall insulating film on the first gate electrode, thermally treating in an oxidizing atmosphere the semiconductor substrate to form a second side wall insulating film on the first gate electrode.

Abstract: A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.

Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.

Abstract: Gate electrodes are formed in a high speed transistor forming region, a low leakage transistor forming region, and a medium voltage transistor forming region, respectively. Thereafter, a photoresist film covering the medium voltage transistor forming region is formed. Then, ions of an impurity are implanted into a semiconductor substrate while using the photoresist film and the gate electrodes as a mask, and p-type pocket regions, extension regions, and impurity regions are thereby formed. Subsequently, another photoresist film covering the high speed transistor forming region is formed. Then, ions of an impurity are implanted into the semiconductor substrate while using the other photoresist film and the gate electrodes as a mask, and impurity regions and extension regions are thereby formed.

Abstract: The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.

Abstract: The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.

Abstract: Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.

Abstract: An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps.

Abstract: The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein only the source region comprises at least one dislocation. The method for forming a transistor according to the present invention comprises forming a mask layer on a semiconductor substrate on which a gate has been formed so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer to only expose at least a portion of a source region; performing a first ion implantation to the exposed portion of the source region; and annealing the semiconductor substrate so as to form a dislocation in the exposed portion of the source region.

Abstract: The invention provides a DMOS transistor in which a leakage current is decreased and the source-drain breakdown voltage of the transistor in the off state is enhanced when a body layer is formed by oblique ion implantation. After a photoresist layer 18 is formed, using the photoresist layer 18 and a gate electrode 14 as a mask, first ion implantation is performed toward a first corner portion 14C1 on the inside of the gate electrode 14 in a first direction shown by an arrow A?. A first body layer 17A? is formed by this first ion implantation. The first body layer 17A? is formed so as to extend from the first corner portion 14C1 to under the gate electrode 14, and the P-type impurity concentration of the body layer 17A? in the first corner portion 14C1 is higher than that of a conventional transistor.

Abstract: A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.

Abstract: In one general aspect, an apparatus can include a substrate, a gate electrode, and a gate dielectric having at least a portion disposed between the gate electrode and the substrate. The apparatus can include a heavily doped drain region disposed within the substrate, and a lightly doped drain region within the substrate and in contact with the heavily doped drain region. The apparatus can also include a medium doped drain region disposed within the lightly doped drain region and having a dopant concentration between a dopant concentration of the heavily doped drain region and a dopant concentration of the lightly doped drain region.

Abstract: Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.

Abstract: A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.

Abstract: The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below.

Abstract: A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.

Abstract: A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.

Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

Abstract: In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.

Abstract: A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

Abstract: A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.

Abstract: The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating film therebetween is provided; an impurity is added to a part of a first region overlapped with the gate electrode with the gate insulating film therebetween in the active layer and a second region but the first region in the active layer by adding the impurity to the active layer from one oblique direction; and the second region is situated in the one direction relative to the first region.

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

Abstract: Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion.

Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

Abstract: An improved method of doping a workpiece is disclosed. In this method, a film comprising the species to be implanted is introduced to the surface of a planar or three-dimensional workpiece. This film can be grown using CVD, a bath or other means. The workpiece with the film is then subjected to ion bombardment to help drive the dopant into the workpiece. This ion bombardment is performed at elevated temperatures to reduce crystal damage and create a more abrupt doped region.

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract: A method for manufacturing a Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has the step of implanting a base region of said MOSFET within an epitaxial layer of a semiconductor chip comprising an insulated gate structure used as a masking element, wherein the implant beam is angled with respect to a vertical axis of the semiconductor chip such that the base region extends sufficiently under the gate to form a Power-MOSFET.

Abstract: A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.

Abstract: An NMOS transistor is formed with improved manufacturability. An embodiment includes forming N-type doped embedded silicon germanium containing carbon (eSiGe:C) in source/drain regions of a substrate, and amorphizing the eSiGe:C. The use of eSiGe:C provides a reduction in extension silicon and dopant loss, improved morphology, increased wafer throughput, improved short channel control, and reduced silicide to source/drain contact resistance.

Abstract: A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

Abstract: Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Abstract: A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.

Abstract: An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions.