Source Or Drain Doping Patents (Class 438/301)
  • Patent number: 10964812
    Abstract: A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: 10910265
    Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace, Tahir Ghani
  • Patent number: 10879377
    Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Cyuan Lu, Tai-Chun Huang
  • Patent number: 10861952
    Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10840373
    Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10755933
    Abstract: Laser light of a short-wavelength laser is irradiated from a rear surface of an n?-type semiconductor substrate, activating a p+-type collector region and an n+-type cathode region. At this time, a surface layer at the rear surface of the n?-type semiconductor substrate is melted and recrystallized, eliminating amorphous parts. Thereafter, laser light of a long-wavelength laser is irradiated from the rear surface of the n?-type semiconductor substrate and an n-type FS region is activated. Substantially no amorphous parts exist in the surface layer at the rear surface of the n?-type semiconductor substrate. Therefore, decreases in the absorption rate and increases in the reflection rate of the laser light of the long-wavelength laser are suppressed and heat from the laser light of the long-wavelength laser is transmitted to the n-type FS region, enabling the n-type FS region to be assuredly activated by laser annealing using lower energy.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura
  • Patent number: 10748994
    Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 10706782
    Abstract: A pixel circuit includes a drive transistor that controls an amount of current to a light-emitting device, and a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor, such that when the second transistor is in an on state the drive transistor becomes diode-connected. A threshold voltage of the drive transistor is compensated during a compensation phase while the drive transistor is diode connected. The light-emitting device is connected between the drive transistor and at a second node to a first voltage input. The pixel circuit further includes a storage capacitor having a first plate connected to the gate of the drive transistor, and a programming capacitor having a first plate connected to a second plate of the storage capacitor, and a second plate of the programming capacitor is electrically connected to a data voltage input during a data programming phase.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 7, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tong Lu, Michael James Brownlow
  • Patent number: 10699913
    Abstract: Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shin-Chi Chen, Jiunn-Hsiung Liao, Yu-Tsung Lai
  • Patent number: 10700181
    Abstract: A FinFET device structure and method for forming the same are provided. The method includes forming a fin structure over a substrate and forming a dummy gate electrode over a middle portion of the fin structure. The method also includes forming a spacer layer on the dummy gate electrode and on the fin structure and performing a plasma doping process on the dummy gate electrode and on the spacer layer. The method further includes performing an annealing process, wherein the annealing process is performed by using a gas comprising oxygen, such that a doped region is formed in a portion of the fin structure, and the spacer layer is doped with oxygen after the annealing process.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Han Huang, Wen-Yen Chen, Jing-Huei Huang
  • Patent number: 10700197
    Abstract: In accordance with some embodiments, a method is provided. The method includes: forming a semiconductor fin protruding from a substrate; depositing a spacer layer over the semiconductor fin; after the depositing the spacer layer over the semiconductor fin, implanting a first dopant in the spacer layer and depositing a dopant layer of the first dopant on the spacer layer in alternating repeating steps; removing the dopant layer; and performing a thermal anneal process to drive the first dopant into the semiconductor fin from the spacer layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Meng-Yueh Liu, Wei-Ken Lin
  • Patent number: 10665717
    Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.
    Type: Grant
    Filed: August 26, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10615276
    Abstract: A vertical field-effect transistor (FET) device and an input/output (IO) FET device are formed. The vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate. Forming the vertical FET device and the IO FET device includes forming a plurality of first fin structures in the vertical FET device area and forming at least two second fin structures in the IO FET device area. The at least two second fin structures are separated by a distance associated with a length of a channel connecting the at least two fin structures in the IO FET device area. The length of the channel is determined based on at least one voltage for implementing the IO FET device.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: 10553723
    Abstract: A method is provided of fabricating a microelectronic device including a semiconductor structure provided with semiconductor bars positioned above one another, the method including the following steps: creating, on a substrate, a stacked structure including an alternation of first bars containing a first material and having a first critical dimension and second bars containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions of the second bars before forming a source and drain block on the portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 4, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Remi Coquand, Nicolas Loubet, Shay Reboh, Robin Chao
  • Patent number: 10546925
    Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 10510886
    Abstract: A method provides a source-drain stressor for a semiconductor device including source and drain regions. Recesses are formed in the source and drain regions. An insulating layer covers the source and drain regions. The recesses extend through the insulating layer above the source and drain regions. An intimate mixture layer of materials A and B is provided. Portions of the intimate mixture layer are in the recesses. The portions of the intimate mixture layer have a height and a width. The height divided by the width is greater than three. A top surface of the portions of the intimate mixture layer in the recesses is free. The intimate mixture layer is reacted to form a reacted intimate mixture layer including a compound AxBy. The compound AxBy occupies less volume than a corresponding portion of the intimate mixture layer.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Ganesh Hegde
  • Patent number: 10497576
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
  • Patent number: 10490661
    Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10480064
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 19, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Delphine Longrie, Antti Juhani Niskanen, Han Wang, Qi Xie, Jan Willem Maes, Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 10468412
    Abstract: A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of transistors. An oxide is deposited over the source and drain of the transistors. A block mask is placed over the first transistor, and the oxide is removed from the second transistor. The block mask is removed and an epitaxial growth is performed on the second transistor. A selective nitridation is performed on the second transistor, and the process is repeated for the first transistor. Other embodiments are also described.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Patent number: 10467134
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Navneeth Kankani, Linh Truong, Sarath Puthenthermadam, Deepanshu Dutta
  • Patent number: 10446654
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate contact structures and self-aligned contact process and methods of manufacture. The structure includes: a gate structure having source and drain regions; a first metal contacting the source and drain regions; a second metal over the first metal in the source and drain regions; and a capping material over the first metal and over the gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10388895
    Abstract: The invention provides an OTFT and manufacturing method thereof. The OTFT comprises: a substrate; a source/drain electrode layer, formed on the substrate; an organic semiconductor layer, formed on the source/drain electrode layer; an organic insulating layer, formed on the organic semiconductor layer; a charge injection layer, formed on the organic insulating layer; a gate electrode layer, formed on the charge injection layer. The invention also provides a corresponding manufacturing method. The OTFT of the invention provides a novel structure for organic thin film transistor to improve the OTFT device stability; the OTFT prepared by the manufacturing method of OTFT of the present invention improves the OTFT device stability.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 20, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Hongyuan Xu
  • Patent number: 10381465
    Abstract: A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 13, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 10347727
    Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 10317716
    Abstract: A display apparatus may include a display panel, a touch electrode, a connecting pad, a first inorganic insulation layer, and a second inorganic insulation layer. The display panel may display an image according to image data. The touch electrode and the connecting pad may be formed of the same conductive material and may be spaced from each other. The first inorganic insulation layer may be positioned between the display panel and the touch electrode and may directly contact each of the touch electrode and the connecting pad. The second inorganic insulation layer may directly contact each of the first inorganic insulation layer and the touch electrode. The touch electrode may be covered by the second inorganic insulation layer. The connecting pad may be positioned between two portions of the second inorganic insulation layer and have a side not covered by the second inorganic insulation layer.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 11, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sooguy Rho
  • Patent number: 10263188
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shu-Jen Han
  • Patent number: 10249741
    Abstract: A flexible ion-selective field effect transistor (ISFET) and methods of making the same are disclosed. The methods may comprise: (a) attaching a flexible substrate to a rigid support with an adhesive; (b) forming an ion-selective field effect transistor structure on a surface of the flexible substrate; and (c) removing the flexible substrate from the rigid support after step (b).
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 2, 2019
    Inventors: Joseph T. Smith, Michael Goryll, Sahil Shah, Jennifer Blain Christen, John Stowell
  • Patent number: 10243056
    Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Kwan Yu, Kyung Ho Kim, Dong Suk Shin
  • Patent number: 10164008
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A plurality of first trench isolations is formed, and at least a part of each of the first trench isolations is formed in a substrate. A plurality of second trench isolations is formed in the substrate after the step of forming the first trench isolations. Each of the first trench isolations is parallel with each of the second trench isolations. One of the second trench isolations is formed between two of the first trench isolations adjacent to each other, and a pitch between the first trench isolations is equal to a pitch between the second trench isolations. The semiconductor structure includes the substrate, the first trench isolations, and the second trench isolations. A material of the first trench isolations is different from a material of the second trench isolations.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: December 25, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 10128114
    Abstract: A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 10090395
    Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 2, 2018
    Assignee: Acorn Technologies, Inc.
    Inventors: Daniel E. Grupp, Daniel J. Connelly
  • Patent number: 10041166
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 7, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Delphine Longrie, Antti Juhani Niskanen, Han Wang, Qi Xie, Jan Willem Maes, Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 9960040
    Abstract: In producing a MOS silicon carbide semiconductor device, after a first heat treatment (oxynitride) is performed in an oxidation atmosphere including nitrous oxide or nitric oxide, a second heat treatment including hydrogen is performed, whereby in the front surface of a SiC epitaxial substrate, a gate insulating film is formed. A gate electrode is formed and after an interlayer insulating film is formed, a third heat treatment is performed to bake the interlayer insulating film. After contact metal formation, a fourth heat treatment is performed to form a reactive layer of contact metal and the silicon carbide semiconductor. The third and fourth heat treatments are performed in an inert gas atmosphere of nitrogen, helium, argon, etc., and a manufacturing method of a silicon carbide semiconductor device is provided achieving a normally OFF characteristic and lowered interface state density.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 1, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Youichi Makifuchi, Mitsuo Okamoto
  • Patent number: 9954101
    Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
  • Patent number: 9871037
    Abstract: A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Yung-Ta Li, Chun-Hsiang Fan, Tung-Ying Lee, Clement Hsing-Jen Wann
  • Patent number: 9865466
    Abstract: Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 9, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Ellie Y. Yieh, Mehul B. Naik, Srinivas D. Nemani
  • Patent number: 9831090
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 9805974
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 31, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 9773728
    Abstract: Some embodiments include memory arrays having rows of fins. Each fin includes a first pedestal, a second pedestal and a trench between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trench between the first and second pedestals. The rows are subdivided amongst deep-type (D) rows and shallow-type (S) rows, with the deep-type rows having deeper channel regions than the shallow-type rows. Some embodiments include rows of fins in which the channel regions along individual rows are subdivided amongst deep-type (D) channel regions and shallow-type (S) channel regions, with the deep-type channel regions being below the shallow-type channel regions.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 26, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9711597
    Abstract: The present invention provides a semiconductor element that can be manufactured easily at a low cost, can obtain a high tunneling current, and has an excellent operating characteristic, a method for manufacturing the same, and a semiconductor integrated circuit including the semiconductor element. The semiconductor element of the present invention is characterized in that the whole or a part of a tunnel junction is constituted by a semiconductor region made of an indirect-transition semiconductor containing isoelectronic-trap-forming impurities.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: July 18, 2017
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Takahiro Mori
  • Patent number: 9698363
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shu-Jen Han
  • Patent number: 9620644
    Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9508727
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
  • Patent number: 9478616
    Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: October 25, 2016
    Assignee: Cree, Inc.
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Lin Cheng, Anant Agarwal
  • Patent number: 9431508
    Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Roman Boschke
  • Patent number: 9406776
    Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 9396940
    Abstract: Embodiments disclosed herein relate to a TFT and methods for manufacture thereof. Specifically, the embodiments herein relate to methods for forming a semiconductor layer at a low temperature for use in a TFT. The semiconductor layer may be formed by depositing a nitride or oxynitride layer, such as zinc nitride or oxynitride, and then converting the nitride layer into an oxynitride layer with a different oxygen content. The oxynitride layer is formed by exposing the deposited nitride layer to a wet atmosphere at a temperature between about 85 degrees Celsius and about 150 degrees Celsius. The exposure temperature is lower than the typical deposition temperature used for forming the oxynitride layer directly or annealing, which may be performed at temperatures of about 400 degrees Celsius.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 19, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Yan Ye
  • Patent number: 9385229
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Xin Lin, Zhihong Zhang, Jiang-Kai Zuo