Radiation Or Energy Treatment Modifying Properties Of Semiconductor Regions Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/308)
  • Patent number: 10395922
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10325983
    Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A source and drain region is positioned at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. The transistor includes a plurality of internal spacers, each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10134782
    Abstract: A thin-film transistor (TFT) array substrate including at least one TFT, the at least one TFT including a semiconductor layer including a source region and a drain region having a first doping concentration on a substrate, a channel region between the source and drain regions and having a second doping concentration, the second doping concentration being lower than the first doping concentration, and a non-doping region extending from the source and drain regions; a gate insulating layer on the semiconductor layer; a gate electrode on the gate insulating layer and at least partially overlapping the channel region; and a source electrode and a drain electrode insulated from the gate electrode and electrically connected to the source region and the drain region, respectively.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Guanghai Jin, Yongjoo Kim, Minhyeng Lee
  • Patent number: 10134602
    Abstract: A process for smoothing a silicon-on-insulator structure comprising the exposure of a surface of the structure to an inert or reducing gas flow and to a high temperature during a heat treatment includes performing a first heat treatment step at a first temperature and under a first gas flow defined by a first flow rate, and performing a second heat treatment step at a second temperature lower than the first temperature and under a second gas flow defined by a second flow rate lower than the first flow rate.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: November 20, 2018
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk, Carole David
  • Patent number: 10103059
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 16, 2018
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yoshiyuki Sugahara, Takashi Tsutsumi, Youichi Makifuchi, Tsuyoshi Araoka, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
  • Patent number: 10090184
    Abstract: A carrier substrate includes: a base substrate; a first coating layer on a first surface of the base substrate; and a second coating layer on a second surface of the base substrate. The thermal expansion coefficients of the first coating layer and the second coating layer are greater than a thermal expansion coefficient of the base substrate, and a thickness of the first coating layer is different from a thickness of the second coating layer.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Min Lee, Young-Sik Yoon, Mu-Gyeom Kim, Mu-Jin Kim, Jae-Hyun Park
  • Patent number: 9911592
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 9812321
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 9793144
    Abstract: A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a multitude of heater lamp tubes is arranged, which directly acts upon the circular wafer carrier plate. Latter is drivingly rotatable about the central axis. A wafer is held on the circular wafer carrier plate by means of a weight-ring residing upon the periphery of a wafer deposited on the wafer carrier plate.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: October 17, 2017
    Assignee: EVATEC AG
    Inventors: Juergen Kielwein, Bart Scholte Von Mast, Rogier Lodder
  • Patent number: 9755057
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Patent number: 9647139
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 9503288
    Abstract: A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a first, a second, a third and a fourth different display interface. The driver is designed to drive respective signals for each of the first, second, third and fourth interfaces through a single output.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Aruna Arun Kumar, Prakash K. Radhakrishnan, Pravas Pradhan, Sunil Kumar C R, Vikas J.
  • Patent number: 9437432
    Abstract: A method of conformally doping a device on a semiconductor workpiece is disclosed. An oxide layer is applied to all surfaces of the device. Further, the thickness of the oxide layer on each surface is proportional to the energy that ions impact that particular surface. For example, ions strike the horizontal surfaces at nearly a normal angle and penetrate more deeply into the workpiece than ions striking the vertical surfaces. After creating an oxide layer that has a variable thickness, a subsequent dopant implant is performed. While ions strike the horizontal surfaces with more energy, these ions pass through a thicker oxide layer to penetrate the workpiece. In contrast, ions strike the vertical surfaces with less energy, but traverse a much thinner oxide layer to penetrate the workpiece. The result is a conformally doped device.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Helen L. Maynard, Deven Raj Mittal, Jun Seok Lee
  • Patent number: 9396951
    Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Malcolm J. Bevan, Haowen Bu, Hiroaki Niimi, Husam N. Alshareef
  • Patent number: 9355965
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 31, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jan {hacek over (S)}ik, Petr Kostelnik, Luká{hacek over (s)} Válek, Michal Lorenc, Milo{hacek over (s)} Pospí{hacek over (s)}il, David Lysá{hacek over (c)}ek, John Michael Parsey, Jr.
  • Patent number: 9355877
    Abstract: A carrier substrate includes: a base substrate; a first coating layer on a first surface of the base substrate; and a second coating layer on a second surface of the base substrate. The thermal expansion coefficients of the first coating layer and the second coating layer are greater than a thermal expansion coefficient of the base substrate, and a thickness of the first coating layer is different from a thickness of the second coating layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 31, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Min Lee, Young-Sik Yoon, Mu-Gyeom Kim, Mu-Jin Kim, Jae-Hyun Park
  • Patent number: 9337288
    Abstract: A method of manufacturing a MOS-type semiconductor device capable of increasing the thickness of a gate oxide film and obtaining high gate withstanding power and reduced switching loss without increasing a gate threshold voltage Vth is provided. A p-type well region is selectively formed on one principle surface of a semiconductor substrate having an n-type low impurity concentration layer by using an oxide film as a mask. Subsequently, a resist mask is formed on the surface of the p-type well region so as to be separated from the oxide film mask, and an n+-type source region is selectively formed from the separation portion. Subsequently, the oxide film mask is removed. Then, an oxide film is formed on the surface of the p-type well region, and the oxide film is removed. Subsequently, a gate electrode coated with a gate oxide film is formed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 10, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Takeyoshi Nishimura
  • Patent number: 9331184
    Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Sheng Yang, Chien-Hung Chen
  • Patent number: 9312270
    Abstract: Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about ?0.1×109 dyne/cm2 to about ?10×109 dyne/cm2 to the substrate.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Tae Jang, Myoungbum Lee, Seungmok Shin, JinGyun Kim, Yeon-Sil Sohn, Seung-Yup Lee, Dae-Hun Choi
  • Patent number: 9209268
    Abstract: The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 8, 2015
    Assignee: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Chenyu Wen, Wei Zhang, Shi-Li Zhang
  • Patent number: 9209175
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
  • Publication number: 20150129974
    Abstract: A semiconductor device includes a first channel, a second channel, a first strained gate electrode including a first lattice-mismatched layer for applying a first stress to the first channel, and a second strained gate electrode including a second lattice-mismatched layer for applying a second stress to the second channel.
    Type: Application
    Filed: March 17, 2014
    Publication date: May 14, 2015
    Applicant: SK HYNIX INC
    Inventor: Yun-Hyuck JI
  • Patent number: 9029226
    Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang, Su-Hao Liu
  • Patent number: 9023706
    Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 5, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 9023741
    Abstract: A method for surface treatment is disclosed which relates to the technical field of producing thin-film devices by printing and solves the problem that the treatment of a substrate surface in the prior art can hardly meet the requirement for printing. The method for surface treatment includes a step of subjecting a surface of a base plate having at least two kinds of substrate patterns formed thereon to a surface treatment for forming a self-assembled monomolecular layer for at least once and a surface treatment by ultraviolet-ozone cleaning, so as to make the difference between the surface energies of the substrate patterns larger or smaller. The method for surface treatment of the invention is suitable for the surface treatment of the substrate surface during producing thin-film devices by printing.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xianghua Wang, Xianfeng Xiong, Longzhen Qiu, Ze Liu
  • Publication number: 20150118817
    Abstract: A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.
    Type: Application
    Filed: May 23, 2014
    Publication date: April 30, 2015
    Inventors: Kiyotaka IMAI, Young-Gwon KIM, Shigenobu MAEDA, Soon-Chul HWANG
  • Patent number: 8975145
    Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yu-Gwang Jeong, Young-Wook Lee, Sang-Gab Kim, Woo-Geun Lee, Min-Seok Oh, Jang-Soo Kim, Kap-Soo Yoon, Shin-Il Choi, Hong-Kee Chin, Seung-Ha Choi, Seung-Hwan Shim, Sung-Hoon Yang, Ki-Hun Jeong
  • Patent number: 8956944
    Abstract: In the transistor including an oxide semiconductor film, which includes a film for capturing hydrogen from the oxide semiconductor film (a hydrogen capture film) and a film for diffusing hydrogen (a hydrogen permeable film), hydrogen is transferred from the oxide semiconductor film to the hydrogen capture film through the hydrogen permeable film by heat treatment. Specifically, a base film or a protective film of the transistor including an oxide semiconductor film has a stacked-layer structure of the hydrogen capture film and the hydrogen permeable film. At this time, the hydrogen permeable film is formed on a side which is in contact with the oxide semiconductor film. After that, hydrogen released from the oxide semiconductor film is transferred to the hydrogen capture film through the hydrogen permeable film by the heat treatment.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Tetsunori Maruyama, Yuta Endo
  • Patent number: 8957357
    Abstract: A solid-state imaging device includes plural photodiodes which are formed in a photodiode area of a unit pixel with no element separating area interposed therebetween and in which impurity concentrations of pn junction areas are different from each other.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Kazuichiro Itonaga
  • Patent number: 8956978
    Abstract: Nanotube devices and approaches therefore involve the formation and/or implementation of substantially semiconducting single-walled nanotubes. According to an example embodiment of the present invention, substantially semiconducting single-walled nanotubes couple circuit nodes in an electrical device. In some applications, semiconducting and metallic nanotubes having a diameter in a threshold range are exposed to an etch gas that selectively etches the metallic nanotubes, leaving substantially semiconducting nanotubes coupling the circuit nodes.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 17, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
    Inventors: Hongjie Dai, Guangyu Zhang, Pengfei Qi
  • Patent number: 8951878
    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiro Jinbo, Hironobu Shoji, Hideto Ohnuma, Shunpei Yamazaki
  • Publication number: 20150028351
    Abstract: A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.
    Type: Application
    Filed: June 5, 2014
    Publication date: January 29, 2015
    Inventors: Edward Robert Van Brunt, Alexander V. Suvorov, Vipindas Pala, Lin Cheng
  • Patent number: 8937005
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 20, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Publication number: 20150001597
    Abstract: A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.
    Type: Application
    Filed: February 21, 2013
    Publication date: January 1, 2015
    Applicant: PRAGMATIC PRINTING LIMITED
    Inventors: Antony Colin Fryer, Richard David Price
  • Patent number: 8921193
    Abstract: The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jocelyn Wei-Yee Teo, Chi-Chun Chen, Shih-Chang Chen
  • Patent number: 8921190
    Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Alvin J. Joseph, Stephen E. Luce, John J. Pekarik, Yun Shi
  • Patent number: 8921178
    Abstract: Improved formation of replacement metal gate transistors is obtained by utilizing a silicon to metal substitution reaction. After removing the dummy gate, a gate dielectric and work function metal are deposited. The work function metal is deposited to a different thickness for the P-channel transistors than for the N-channel transistors. A sacrificial polysilicon gate is then formed, which is caused to undergo substitution with a metal such as aluminum.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kenzo Manabe
  • Patent number: 8912104
    Abstract: An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: December 16, 2014
    Assignee: Altera Corporation
    Inventors: Deepa Ratakonda, Christopher J. Pass, Che Ta Hsu, Fangyun Richter, Wilson Wong
  • Publication number: 20140363944
    Abstract: A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Application
    Filed: July 17, 2014
    Publication date: December 11, 2014
    Inventors: Anh Duong, Clemens Fitz, Olov Karlsson
  • Patent number: 8906704
    Abstract: A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8906742
    Abstract: Systems and methods are disclosed for performing laser annealing in a manner that reduces or minimizes wafer surface temperature variations during the laser annealing process. The systems and methods include annealing the wafer surface with first and second laser beams that represent preheat and anneal laser beams having respective first and second intensities. The preheat laser beam brings the wafer surface temperate close to the annealing temperature and the anneal laser beam brings the wafer surface temperature up to the annealing temperature. The anneal laser beam can have a different wavelength, or the same wavelength but different orientation relative to the wafer surface. Reflectivity maps of the wafer surface at the preheat and anneal wavelengths are measured and used to select the first and second intensities that ensure good anneal temperature uniformity as a function of wafer position. The first and second intensities can also be selected to minimize edge damage or slip generation.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Ultratech, Inc.
    Inventors: Xiaohua Shen, Yun Wang, Xiaoru Wang
  • Patent number: 8900952
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8877619
    Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 4, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Lance Scudder, Dalong Zhao, Teymur Bakhisher, Sameer Pradhan
  • Patent number: 8865501
    Abstract: The object of the present invention is to provide a method of fabricating a thermoelectric material and a thermoelectric material fabricated thereby. According to the present invention, since carbon nanotubes with no surface treatment are dispersed in the alloy, electrical resistivity decreases and electrical conductivity increases in comparison to surface-treated carbon nanotubes and an amount of thermal conductivity decreased is the same as that in the case of using surface-treated carbon nanotubes, and thus, a ZT value, a thermoelectric figure of merit, is improved. A separate reducing agent is not used and an organic solvent having reducing powder is used to improve economic factors related to material costs and process steps, and carbon nanotubes may be dispersed in the thermoelectric material without mechanical milling.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 21, 2014
    Assignee: Korea Institute of Machinery and Materials
    Inventor: Kyung Tae Kim
  • Patent number: 8854614
    Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Kang, Taegon Kim, Hanmei Choi, Eunyoung Jo, Gonsu Kang, Sungho Kang, Sungho Heo
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20140287565
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) providing a substrate (100); b) forming a dummy gate stack on the substrate (100), wherein the dummy gate stack consists of a gate dielectric layer (203) and a dummy gate (201) located on the gate dielectric layer (203), and the material of the dummy gate (201) is amorphous Si; c) performing ion implantation to regions exposed on both sides of the dummy gate (201) on the substrate (100), so as to form source/drain regions (110); d) forming an interlayer dielectric layer (400) that covers the source/drain regions (110) and the dummy gate stack; e) removing part of the interlayer dielectric layer (400) to expose the dummy gate (201) and removing the dummy gate (201); and f) annealing to activate dopants in source/drain regions.
    Type: Application
    Filed: December 2, 2011
    Publication date: September 25, 2014
    Inventors: Haizhou Yin, Weize Yu
  • Patent number: 8841194
    Abstract: In one aspect, a method of forming a polysilicon (poly-Si) layer and a method of manufacturing a thin film transistor (TFT) using the poly-Si layer is provided. In one aspect, the method of forming a polysilicon (poly-Si) layer includes forming an amorphous silicon (a-Si) layer on a substrate in a chamber; cleaning the chamber; removing fluorine (F) generated while cleaning the chamber; forming a metal catalyst layer for crystallization, on the a-Si layer; and crystallizing the a-Si layer into a poly-Si layer by performing a thermal processing operation.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Ryuk Park, Yun-Mo Chung, Tak-Young Lee, Kil-Won Lee
  • Patent number: 8835800
    Abstract: The present invention provides a laser irradiation apparatus which can accurately control positions of beam spots of laser beams emitted from laser oscillators and the distance between the adjacent beam spots. A laser irradiation apparatus of the present invention includes a first movable stage with an irradiation body provided, two or more laser oscillators emitting laser beams, a plurality of second movable stages with the laser oscillators and optical systems provided, and a means for detecting at least one alignment maker. The first stage and the second stages may move not only in one direction but also in a plurality of directions. Further, the optical systems are to shape the laser beams emitted from the laser oscillators into linear beams on the irradiation surface.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Yoshiaki Yamamoto
  • Patent number: 8828834
    Abstract: One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shesh Mani Pandey, Shiang Yang Ong, Jan Hoentschel